External Sync And Sync From Hdmi Section; Signals Routing To Synchronization Channels; Figure 86: External/Hdmi Syncs Routing To Cp Section - Analog Devices ADV7850 Hardware Manual

sync_ch2_emb_sync_sel[1:0], IO, Address 0x08[1:0]
This control is used to select from the outputs of the two sync slicers as input to sync channel 2.
Function
sync_ch2_emb_sync_se
l[1:0]
00 
01
10
11

External Sync and Sync from HDMI Section

9.6.2
The CP section can receive syncs from the external HSync, VSync and CSync inputs or from the HDMI section, as shown in
The external sync signals from the HDMI are used for STDI detection. Note also that
embedded sync signals, EMB_SYNC_1 and EMB_SYNC_2, which are output by the sync slicers.
H S / C S _ I N 1
H S / C S _ I N 2
HD M I H S
VS _ I N 1
VS _ I N 2
HD M I V S

9.6.2.1 Signals Routing to Synchronization Channels

The ADV7850 has two synchronization channels. Each channel consists of one SSPD and one STDI section. When an HDMI input is
applied, the HDMI core will generate HSync, VSync, and DE signals and supply them as input to each synchronization channel shown in
Figure 86. HSync from the HDMI block is denoted as HDMI_HS, and VSync from the HDMI block is denoted as HDMI_VS. As well as
the HDMI sync signals, external CSync or HSync and VSync signals applied to the pins are provided as inputs to the HSync and VSync
muxes.
Rev. A May 2012
Description
emb_sync_sel2
emb_sync_sel1
emb_sync_sel2
Tie to GND
P R I M_M O D E [ 2 ]
0
1 0 0
0 1
1 0 H S / C S 1
1 1
H S / C S 2
SY NC _ CH 1 _ H S _ SE L [ 1 : 0 ]
0 0
0 1
1 0
1 1
E M B _ SY NC _ 1
SY NC _ CH 2 _ H S _ SE L [ 1 : 0 ]
P R I M_M O D E [ 2 ]
0
1 0 0 E M B _ SY NC _ 2
0 1
1 0
1 1
SY NC _ CH 1 _ VS _ SE L [ 1 : 0 ]
0 0 VS 1
0 1
1 0 VS 2
1 1
SY NC _ CH 2 _ VS _ SE L [ 1 : 0 ]

Figure 86: External/HDMI Syncs Routing to CP Section

Figure 86
H S / C S 1
H S / C S 1 _ G R SSP D 1
VS 1
VS 1 _ G R
P O L A R I T Y
E M B _ SY NC _ 1 C O RR E C T IO N
E M B _ SY NC _ 1 _ G R
HS1_GR_PC
S T D I 1
VS1_GR_PC
E M BE DD E D _
SY NC _M O D E1
HS2_GR_PC
S T D I 2
VS2_GR_PC
E M BE DD E D _
SY NC _M O D E2
H S / C S 2
H S / C S 2 _ G R SSP D 2
VS 2
VS 2 _ G R
P O L A R I T Y
E M B _ SY NC _ 2 C O RR E C T IO N
E M B _ SY NC _ 2 _ G R
D IG _ SY NC _ D E G L I T CH _ R E DUC E
D IG SY NC D E G L I T CH R E DUC E M A N
259
shows the routing of the internal
SYNC_CH_AUTO_MODE
SY NC _ CH 1 _ P R IO R I T Y
CH1_SSPD_PP_EN
CH 1 _ SY NC _ S RC [ 1 : 0 ]
CH 1 _ SSP D _ C O N T
CH 1 _ T R IG _ SSP D
CH 1 _ P O L _M A N _ E N
CH 1 _ P O L _ H S C S
CH 1 _ P O L _ V S
T O SY NC
H S _ P C
H S 1 _ P C
VS 1 _ P C
H S 2 _ P C
VS 2 _ P C
T O SY NC
VS _ P C
T O SY NC
E M BE DD E D _
SY NC _M O D E
CH2_SSPD_PP_EN
CH2_SYNC_SRC[1:0]
CH2_SSPD_CONT
CH 2 _ T R IG _ SSP D
CH 2 _ P O L _M A N _ E N
CH 2 _ P O L _ H S C S
CH 2 _ P O L _ V S
ADV7850
Figure 86.