Standard Detection And Identification - Analog Devices ADV7850 Hardware Manual

Function
sspd_rslt_chngd_ch1_st
0 
1
sspd_rslt_chngd_ch1_raw, IO, Address 0x5B[0] (Read Only)
Status of the SSPD Result Changed on sync channel 1 interrupt signal. When set to 1 it indicates a change in SSPD result of the
currently selected sync channel. A change in SSPD result can be either due to a polarity or source change. Once set, this bit will remain
high until it is cleared via sspd_rslt_chngd_ch1_clr.
Function
sspd_rslt_chngd_ch1_r
aw
0 
1
sspd_rslt_chngd_ch2_st, IO, Address 0x5C[4] (Read Only)
This readback indicates the latched signal status of the SSPD result changed for sync channel 2 interrupt signal. Once set, this bit
remains high until the interrupt is cleared via sspd_rslt_chngd_ch2_clr. This bit is only valid if enabled via the corresponding INT1 or
INT2 interrupt mask bit.
Function
sspd_rslt_chngd_ch2_st
0 
1
sspd_rslt_chngd_ch2_raw, IO, Address 0x5B[4] (Read Only)
This readback indicates the status of the SSPD result changed on sync channel 2 interrupt signal. When set to 1, it indicates a change in
SSPD result of the currently selected sync channel. A change in SSPD result can be either due to a polarity or source change. Once set,
this bit will remain high until it is cleared via sspd_rslt_chngd_ch1_clr.
Function
sspd_rslt_chngd_ch2_r
aw
0 
1

Standard Detection and Identification

9.7.2
As shown in Figure 86, the two synchronization processing channels also contain Standard Detection and Identification (STDI) blocks.
These monitor the synchronization signals to determine the video input standard.
The STDI blocks perform four key measurements:
• Block Length chx_bl[13:0]
This is the number of 27 MHz clock cycles (XTAL frequency) in a block of eight lines. From this, the time duration of one line
can be concluded.
• Line Count in Field chx_lcf[10:0]
The chx_lcf[10:0] readback value is the number of lines between two VSyncs, that is, over one field measured by channel x.
• Line Count in VSync chx_lcvs[4:0]
The lcvs[4:0] readback value is the number of lines within one VSync period.
• Field Length chx_fcl[12:0]
This is the number of 27 MHz clock cycles in a 1/256
Rev. A May 2012
Description
No SSPD result changed for sync channel 1 interrupt event occurred
SSPD result changed for sync channel 1 interrupt event occurred
Description
No change in SSPD result for sync channel 1
Change occurred in SSPD result for sync channel 1
Description
No SSPD result changed for sync channel 2 interrupt event occurred
SSPD result changed for sync channel 2 interrupt event occurred
Description
No change in SSPD result for sync channel 2
Change occurred in SSPD result for sync channel 2
th
of a field. Alternately, this value of FCL multiplied by 256 gives one field
271
ADV7850