All registers specified in table are located in the Repeater Map.
1
7.39 INTERFACE TO DCM SECTION
The video data from the HDMI section is sent to the CP section via the DCM block. The video data output by the HDMI section is always
in a 4:4:4 format with 36 bits per pixel. This is irrespective of the encoding format of the video data encapsulated in the HDMI/DVI
stream input to the HDMI receiver section (that is, 4:2:2 or 4:4:4).
•
If the HDMI section receives a stream with video encoded in a 4:4:4 format, it passes the video data to the DCM section.
•
If the HDMI section receives a stream with video encoded in a 4:2:2 format (refer to
the video data into a 4:4:4 format, according to the
section (refer to
Figure
•
If the HDMI receiver receives video data with fewer than 12 bits used per channel, the valid bits are left-shifted on each
component channel with zeroes padding the bit below the LSB before being sent to the DCM section.
TMDS
Channel
Rev. A May 2012
KSV Byte
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
75).
Y
/ Cb
0
0
Bit 3-0
Y
bits 3-0
0
0
Cb
bits 3-0
Bit 7-4
0
Y
bits 11-4
1
Bit 7-0
0
Cb
bits 11-4
2
Bit 7-0
0
Figure 74: YC
Register Name
Address
ksv_byte106
EA
ksv_byte107
EB
ksv_byte108
EC
ksv_byte109
ED
ksv_byte110
EE
ksv_byte111
EF
ksv_byte112
F0
ksv_byte113
F1
ksv_byte114
F2
ksv_byte115
F3
ksv_byte116
F4
ksv_byte117
F5
ksv_byte118
F6
ksv_byte119
F7
ksv_byte120
F8
ksv_byte121
F9
ksv_byte122
FA
ksv_byte123
FB
ksv_byte124
FC
ksv_byte125
FD
ksv_byte126
FE
ksv_byte127
FF
up_conversion_mode
Y
/ Cr
Y
/ Cb
1
0
2
2
Y
bits 3-0
Y
bits 3-0
1
2
Cr
bits 3-0
Cb
bits 3-0
0
2
Y
bits 11-4
Y
bits 11-4
1
2
Cr
bits 11-4
Cb
bits 11-4
0
2
C
4:2:2 Video Data Encapsulated in HDMI Stream
b
r
221
1
Figure
74), the HDMI section upconverts
bit, and passes the upconverted video data to the DCM
Y
/ Cr
Y
/ Cb
3
2
4
4
Y
bits 3-0
Y
bits 3-0
3
4
Cr
bits 3-0
Cb
bits 3-0
2
4
Y
bits 11-4
Y
bits 11-4
3
4
Cr
bits 11-4
Cb
bits 11-4
2
4
ADV7850
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