ADV7850 stores an address counter for each DDC port that maintains the value of the subaddress that was last accessed. The
address counter is incremented by 1 every time a read or a write access is requested on the DDC port.
CURRENT ADDRESS
READ SEQUENCE
I
C Protocols for Access to HDCP Registers
2
14.2.2
An I
C master connected on a DDC port can access the internal HDCP controller using the following protocol:
2
•
Write sequence, as defined in Section
•
Read sequence, as defined in Section
•
Short read format, as defined in the High-bandwidth Digital Content Protection (HDCP) System Specifications
DDC Port A
14.2.3
The DDC lines of the HDMI port A comprise the DDCA_SCL and DDCA_SDA pins. An HDMI host connected to the DDC port A
accesses the internal E-EDID at address 0xA0 in read only mode, and the HDCP registers at address 0x74 in read/write mode (refer to
Figure
140). The internal E-EDID for port A is described in Section 7.9.
Refer to the High-bandwidth Digital Content Protection (HDCP) System Specifications for detailed information on the HDCP registers.
(SA = Slave Address)
DDC Port B
14.2.4
The DDC lines of the HDMI port B comprise the DDCB_SCL and DDCB_SDA pins. An HDMI host connected to the DDC port B
accesses the internal E-EDID at address 0xA0 in read-only mode, and the HDCP registers at address 0x74 in read/write mode (refer to
Figure
141). The internal E-EDID for port B is described in Section
Refer to the High-bandwidth Digital Content Protection (HDCP) System Specifications for detailed information on the HDCP registers.
Rev. A May 2012
LSB = 1
s
SLAVE ADDR
DATA(1)
A(S)
S= START BIT
A(S) = ACKNOWLEDGE BY SLAVE
P = STOP BIT
A(M) NO-ACKNOWLEDGE BY MASTER
Figure 139: Current Address Read Sequence
14.1.2
14.1.2
Figure 140: Internal E-EDID and HDCP Registers Access from Port A
Figure 141: Internal E-EDID and HDCP Registers Access from Port B
...
A(S)
7.10.
390
ADV7850
DATA(N)
A(M)
P
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