Tristate Pins; Adc Phase Control; Adc-Hdmi Simultaneous Mode - Analog Devices ADV7850 Hardware Manual

Function
sdp_reset
0 
1
sdp_mem_reset, IO, Address 0xFF[2] (Self-Clearing)
This control is used to apply a memory interface reset. This is a self clearing bit.
Function
sdp_mem_reset
0 
1
tx_soft_reset, IO, Address 0x1B[7] (Self-Clearing)
This control is used for software reset of the HDMI Tx. This is a self clearing bit.
Function
tx_soft_reset
1

Tristate Pins

3.3.3
tri_audio, IO, Address 0x15[4] (Self-Clearing)
This control is used to apply a memory interface reset. This is a self clearing bit.
Function
TRI_AUDIO
0 <<
1

ADC Phase Control

3.3.4
dll_phase[5:0], Addr 4C (DPLL), Address 0xC8[5:0]
This control is used to adjust the phase of the ADC clocks in CP modes.
Function
dll_phase[5:0]
000000 <<
xxxxxx

3.4 ADC-HDMI SIMULTANEOUS MODE

The ADV7850 can be configured to be in either simultaneous mode or non simultaneous mode, as follows:
• Simultaneous mode
In this mode, specific subsections of the HDMI block remain enabled when the ADV7850 is programmed to process analog
inputs through the CP and SD core. Simultaneous mode keeps the HDCP engine and the E-EDID/Repeater controller active,
allowing an upstream transmitter to authenticate the ADV7850 even when the latter is in analog mode. Keeping the HDCP
engine active allows for fast switching from analog mode to HDMI mode, as the transmitter will have already authenticated the
ADV7850 when the latter is switched into HDMI mode. Simultaneous mode is also used for SDP and HDMI audio mode (refer
to Section 4.2.)
Rev. A May 2012
Description
Not reset
Apply SDP reset
Description
Not reset
Apply SDP memory reset
Description
Software reset to Tx block
Description
Audio output pins active
Tristate audio output pins
Description
Default
Adjust phase of clock in CP modes
34
ADV7850