Video Setup; Input Format; Video Mode Detection; Figure 123: Format Of Video Data Input Into Hdmi Tx Core - Analog Devices ADV7850 Hardware Manual

hdcp_controller_error[3:0]
in the HDCP/EDID controller error field even when the interrupt is cleared.
hdcp_controller_error[3:0], Addr B8 (Main), Address 0xC8[7:4] (Read Only)
This readback indicates the HDCP error information.
Function
hdcp_controller_error[3
:0]
0000 
0001
0010
0011
0100
0101
0110
0111
1000

13.11 VIDEO SETUP

Input Format

13.11.1
The HDMI Tx core of the ADV7850 receives video data from the ADV7850 digital core via a 36-bit wide bus and four synchronization
signals; the pixel clock, the data enable, the horizontal and the vertical synchronization signals. The HDMI Tx core always receives the
video data in a 4:4:4 and SDR format.
Component
Channel
Y
Cb
Cr

Video Mode Detection

13.11.2
The video mode detection feature can inform the user of the CEA 861 defined Video Identification Code (VIC) of the video being input
to the Tx core, as well as some additional formats. If a CEA 861 format is detected, the VIC is contained in vfe_fmt_vid[5:0]. Some
additional non CEA 861 formats are contained in vfe_aux_vid[2:0].
For some standards for which the VIC cannot be detected, the user needs to configure the following registers:
• The aspect ratio (set via asp_ratio) is used to distinguish between CEA 861 video timing codes where the aspect ratio is the only
difference.
• For 240p and 288p modes, the number of total lines can be selected in vfe_prog_mode[1:0].
•
The VIC detected is also affected by the pixel repetition.
The detected VIC is sent in the AVI InfoFrames unless pixel repetition is applied to the video stream transmitted by the ADV7850. When
pixel repetition is applied to the video data, the VIC sent in the AVI InfoFrame may be different as the VIC is automatically determined by
the ADV7850. To override the VIC detection, the pixel repetition mode must be set to manual by setting
The desired VIC is then set. The Tx core can support non CEA 861 formats but the VIC will not be automatically detected for these
Rev. A May 2012
status field. The error code is only valid when
Description
No error
Bad receiver Bksv
Ri mismatch
Pj mismatch
I2C error (usually a no-ack)
Time out waiting for downstream repeater
Maximum cascade of repeaters exceeded
SHA-1 hash check of KSV list failed
Too many devices connected to repeater tree
Pixel
0
G/Y
Bit 12-0
0
B/Cb
Bit 12-0
0
R/Cr
Bit 12-0
0

Figure 123: Format of Video Data Input into HDMI Tx Core

hdcp_error_interrupt
Pixel Pixel
1 2
G/Y G/Y
1 2
B/Cb B/Cb
1 2
R/Cr R/Cr
1 2
356
is set to 1. The last error code will remain
Pixel Pixel
3 4
G/Y G/Y
3 4
B/Cb B/Cb
3 4
R/Cr R/Cr
3 4
pr_mode[1:0]
ADV7850
...
...
...
...
to 0b10 or 0b11.