Figure 89: Sspd Vsync And Hsync Monitoring Operation - Analog Devices ADV7850 Hardware Manual

Function
ch2_vs_act
0 
1
The SSPD section continuously monitors the VSync input signal over timing windows of 2
ch2_vs_act is updated at the end of each window as follows:
• ch2_vs_act is set to 1 if the SSPD detected four edges or two periods on the VSync signal
•
ch2_vs_act is set to 0 if the SSPD detected less than four edges or two periods on the VSync signal
2 22 crystal clock cycles window
ch1_rs_active, Addr 44 (CP), Address 0xB5[2] (Read Only)
This readback indicates activity in the embedded synchronization signal input to sync channel 1 SSPD. ch1_sspd_pp_en must be set to
1 and ch1_sspd_dvalid must return 1 for this readback to be valid.
Function
ch1_rs_active
0 
1
ch2_rs_active, Addr 44 (CP), Address 0x4F[2] (Read Only)
This readback displays activity in an embedded synchronization signal input to sync channel 2 SSPD. ch2_sspd_pp_en must be set to 1
and ch2_sspd_dvalid must return 1 for this readback to be valid. This readback is only valid when there is an HSync and VSync signal
present. It is not valid to use this control when only an embedded signal is present. The purpose of this control is to indicate that the
user can switch to embedded sync if using HSync and VSync inputs.
Function
ch2_rs_active
0 
1
Notes:
•
It is possible to monitor changes in ch1_vs_act, ch1_hs_act and ch1_rs_activE via the
• Likewise, it is possible to monitor changes in ch2_vs_act, ch2_hs_act, and ch2_rs_active via the
interrupt status.
sspd_rslt_chngd_ch1_st, IO, Address 0x5C[0] (Read Only)
This readback indicates the latched signal status of the SSPD result changed for sync channel 1 interrupt signal. Once set, this bit
remains high until the interrupt is cleared via sspd_rslt_chngd_ch1_clr. This bit is only valid if enabled via the corresponding INT1 or
INT2 interrupt mask bit.
Rev. A May 2012
Description
No activity detected on VSync input to sync channel 2 SSPD
VSync input to sync channel 2 SSPD carries an active signal
Field 3 or Line 3
Field 4 or Line 4
SSPPD monitors activity on each sync signal VS and HS over a 2

Figure 89: SSPD VSync and HSync Monitoring Operation

Description
Activity detected on embedded signal input to sync channel 1 SSPD
No activity detected on embedded signal input to sync channel 1 SSPD
Description
Activity detected on embedded signal input to sync channel 2 SSPD
No activity detected on embedded signal input to sync channel 2 SSPD
crystal clock periods (refer to
22
Field 5 or Line 5
Field 6 or Line 6
22 crystal clock cycles window
270
Field 7 or Line 7
2 22 crystal clock cycles window
sspd_rslt_chngd_ch1_st interrupt status.
sspd_rslt_chngd_ch2_st
ADV7850
Figure 89).