cp_reg_ff
Bit Name
Bit Number
0
Reserved
1
Reserved
2
Reserved
3
Reserved
4
cp_free_run
5
Reserved
6
mv_agc_det
7
mv_ps_det
Note: For Bit 7 and Bit 6 to be meaningful, the Macrovision PS and AGC detection circuitry must be enabled (on by default).
cp_free_run, Addr 44 (CP), Address 0xFF[4] (Read Only)
This readback indicates the component processor free run status.
Function
cp_free_run
0
1
mv_agc_det, Addr 44 (CP), Address 0xFF[6] (Read Only)
This readback indicates the Macrovision AGC pulses detection status.
Function
mv_agc_det
0
1
mv_ps_det, Addr 44 (CP), Address 0xFF[7] (Read Only)
This readback indicates the Macrovision pseudo pulses detection status.
Function
mv_ps_det
0
1
9.14
AUTO GRAPHICS MODE
Auto graphics mode is designed to allow the user to configure the ADV7850 to accept an input format not shown in
minimum amount of effort. Auto graphics mode is not limited only to graphics input, it can also be used to support component video
input.
Primary Auto Graphics Controls
9.14.1
The user must provide the following key parameters to enable the ADV7850 to sample correctly the incoming video signal:
•
pll_div_man_en
This bit must be set to allow a user programmable PLL divide ratio to be used.
•
pll_div_ratio[12:0]
The PLL divide ratio is equal to the number of samples per line. The ADV7850 multiplies the incoming HSync frequency by the
PLL divide ratio to generate the sampling clock.
•
ch1_fr_ll[10:0]/ch2_fr_ll[10:0]
Rev. A May 2012
Description
CP is free running (no valid video signal found)
Detected Macrovision AGC pulses
Detected Macrovision pseudo synchronization pulses
Description
CP not free running
CP free running
Description
Macrovision AGC pulses not detected by CP
CP detected Macrovision AGC pulses
Description
No Macrovision pseudo synchronization pulses detected
Detected Macrovision pseudo synchronization pulses
305
ADV7850
Table 2
with the
Need help?
Do you have a question about the ADV7850 and is the answer not in the manual?
Questions and answers