Analog Devices ADV7850 Hardware Manual page 157

Function
tmds_pll_locked
0 
1
tmdspll_lck_a_raw, IO, Address 0x6A[7] (Read Only)
This readback indicates the raw status of the Port A TMDS PLL lock signal.
Function
tmdspll_lck_a_raw
0 
1
tmdspll_lck_b_raw, IO, Address 0x6A[6] (Read Only)
This readback indicates the raw status of the Port B TMDS PLL lock signal.
Function
tmdspll_lck_b_raw
0 
1
tmdspll_lck_c_raw, IO, Address 0x6A[5] (Read Only)
This readback indicates the raw status of the Port C TMDS PLL lock signal.
Function
tmdspll_lck_c_raw
0 
1
tmdspll_lck_d_raw, IO, Address 0x6A[4] (Read Only)
This readback indicates the raw status of the Port D TMDS PLL lock signal.
Function
tmdspll_lck_d_raw
0 
1
new_tmds_frq_raw, IO, Address 0x83[1] (Read Only)
This readback indicates the status of the new TMDS frequency interrupt signal. When set to 1, it indicates the TMDS frequency has
changed by more than the tolerance set in freqtolerance[3:0]. Once set, this bit remains high until it is cleared via new_tmds_freq_clr.
Function
new_tmds_frq_raw
0 
1
freqtolerance[3:0], Addr 68 (HDMI), Address 0x0D[3:0]
This control is used to set the tolerance in MHz for a new TMDS frequency detection. This tolerance is used for the audio mute mask
mt_msk_vclk_chng and the HDMI status bit new_tmds_frq_raw.
Rev. A May 2012
Description
TMDS PLL not locked
TMDS PLL locked to TMDS clock input of selected HDMI port
Description
TMDS PLL on Port A not locked
TMDS PLL on Port A locked to incoming clock
Description
TMDS PLL on Port B not locked
TMDS PLL on Port B locked to incoming clock
Description
TMDS PLL on Port C not locked
TMDS PLL on Port C locked to incoming clock
Description
TMDS PLL on Port D not locked
TMDS PLL on Port D locked to incoming clock
Description
TMDS frequency not changed by more than tolerance set in freqtolerance[3:0] in HDMI Map
TMDS frequency changed by more than tolerance set in freqtolerance[3:0] in HDMI Map
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ADV7850