sdp_aclp_speed[4:0] determines the time constant of the analog clamp circuitry. It is important to realize that the analog clamp reacts
quickly to correct any residual DC level error for the active line.
This register also allows the user to freeze the analog clamp loop at any point in time.
By default, the time constant of the digital clamp is adjusted dynamically to suit the currently connected input signal.
5.3 ANALOG INPUT MUXING
The ADV7850 has thirteen analog input pins, Ain1 to Ain13. The user must select the Ain pin signals routed to the ADC in order to
process the video signals that appear on the analog inputs. The ADV7850 has an integrated analog muxing section to route the video
signals to the ADCs. This allows more than one source of video signal to be connected to the decoder and routes the desired video signals
to the ADCs. A selection of predefined routing options are available and are controlled by the ain_sel[2:0]; this is referred to as automatic
input muxing selection. It is also possible to manually select routing of analog inputs to individual ADCs; this is referred to as manual
input muxing.
Analog Input Routing Recommendation
5.3.1
ADI has specific Ain pin recommendations for specific video processing modes in order to ensure the best performance. ADI
recommends the following:
•
RGB Graphics − Ain 1, 2, 3
•
Component − Ain 4, 5, 6
•
SCART RGB − Ain 7, 8, 9
•
SCART CVBS – Ain 10
•
CVBS 1 – Ain12
•
YC – Ain 10, 11
•
CVBS 2 – Ain13
Refer to Section
15.
Rev. A May 2012
Figure 9: ADV7850 Typical Configurations
45
ADV7850
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