Final Sync Muxing Stage; Synchronization Processing Channel Mux; Figure 87: Final Sync Muxing Stage - Analog Devices ADV7850 Hardware Manual

This glitch filter is not controllable.

Final Sync Muxing Stage

9.6.3
As described in Section 9.6, the main source for sync information into the CP core is the SSPD block.
muxing, which selects the syncs to be used in the CP core.
HSync and VSync signals from the selected SSPD block are passed through the glitch rejection filters. Then, depending on whether or not
the input was an embedded sync signal type (external CS or SOG/SOY), VS is generated by the VSync slicer block.
For CS/SOG/SOY input types, the embedded sync signal must be sliced to find the VS signal, but this should not be done for separate HS
and VS inputs. Therefore, the EMBEDDED_SYNC_MODE control signal that is sent from the SSPD block is used to control a mux to
bypass the VSync slicer block when the input is external HSync and VSync.
HS_PC
VS_PC

9.7 SYNCHRONIZATION PROCESSING CHANNEL MUX

The ADV7850 has two synchronization processing channels, as shown in
receives synchronization, as described in Section 9.6.2.1.
As explained in Section 9.6.2.1, channel 1 and channel 2 are identical in that they consist of the same basic SSPD and STDI blocks.
However, they differ in the way in which the signals are multiplexed so that any synchronization source can be routed to any of the
synchronization channels. By default, the synchronization channels are configured into the following two sets:
• Set 1: HS_IN1, VS_IN1, HDMI_HS and EMB_SYNC_1 feed synchronization channel 1
• Set 2: HS_IN2, VS_IN2, HDMI_VS and EMB_SYNC_2 feed synchronization channel 2
The registers that control the synchronization signals routed to each synchronization channel are described in Section
Section 9.6.2.1. The output from one synchronization channel is used to provide timing to the CP core.. The method for determining the
sync channel used to output synchronization signals to the CP core is selected by sync_ch_auto_mode. This bit is used to enable and
disable the channel auto mode and works in conjunction with sync_ch1_priority, as follows:
sync_ch_auto_mode = 0
•
The priority of the channels is determined by sync_ch1_priority:

sync_ch1_priority = 1: Select channel 1

sync_ch1_priority = 0: Select channel 2
sync_ch_auto_mode = 1
•
The synchronization channel that outputs sync signals to the CP core is automatically selected and based on the free run status
of each channel. The priority of selection is determined by sync_ch1_priority:

sync_ch1_priority = 1: Priority for channel 1 – free run if both channels are in free run and monitor channel 1.

sync_ch1_priority = 0: Priority for channel 2 – free run if both channels are in free run and monitor channel 2.
Rev. A May 2012
HSYNC
GLITCH
REJECTION
FILTER
VSYNC
VSYNC
GLITCH
REJECTION SLICER
FILTER

Figure 87: Final Sync Muxing Stage

Figure
262
Figure 87
TO CP CORE
EMBEDDED_SYNC_MODE
1
TO CP CORE
0
86. These contain SSPD and the STDI functionality that
ADV7850
shows the final stage of
9.6.1 and