Audio Dpll; Locking Mechanism; Acr Parameters Loading Method; Figure 61: Audio Processor Block Diagram - Analog Devices ADV7850 Hardware Manual

TM DS Clock
Data from HDCP
Engine/Mask

Audio DPLL

7.25.1
The audio DPLL generates an internal audio master clock with a frequency of 128 times the audio sampling frequency, usually called fs.
The audio master clock is used to clock the audio processing section.

Locking Mechanism

7.25.2
When the upstream HDMI transmitter outputs a stable TMDS frequency and consistent audio clock regeneration values, the audio DPLL
locks within two cycles of the audio master clock after the following two conditions are met:
• TMDS PLL is locked (refer to tmds_pll_locked)
• ADV7850 has received an ACR packet with the N and CTS parameters within a valid range
The audio DPLL lock status can be monitored via audio_pll_locked.
audio_pll_locked, Addr 5C (audio_codec), Address 0x0D[0] (Read Only)
This readback indicates the audio PLL locking status.
Function
audio_pll_locked
0 
1

ACR Parameters Loading Method

7.25.3
The N and CTS parameters from the ACR packets are used to regenerate the audio clock and are reloaded into the DPLL any time they
change. The self-clearing bit
from the ACR packet into the audio DPLL.
force_n_update, Addr 68 (HDMI), Address 0x5A[0] (Self-Clearing)
This control is used to force an N and CTS value update to the audio DPLL. The audio DPLL regenerates the audio clock. This is a self
clearing bit.
Function
force_n_update
0 
1
Rev. A May 2012
ACR Packet
Data
Packet Process or
(Dispatch Block)

Figure 61: Audio Processor Block Diagram

Description
Unlocked
Locked
force_n_update provides a means to reset the audio DPLL by forcing a reload of the N and CTS parameters
Description
No effect
Force update on N and CTS values for audio clock regeneration
TM DS Clock
Audio D P L L
N
CTS
Audio Data
To D P P
Video Data
Block
178
HA_MCLK
128fs
Audio
Reconstruction
Audio
Serialization
FIF O
M uxing
Ch ann el St atus
Bits Collection
ADV7850
HA_P0
HA_P1
HA_P2
HA_P3
HA_P4
HA_P5
HA_SCLK