Stdi Usage; Stdi Readback Values For Sd, Pr, And Hd; Figure 94: Stdi Usage Flowchart; Table 53: Stdi Readback Values For Sd, Pr, And Hd - Analog Devices ADV7850 Hardware Manual

Function
ch1_stdi_intlcd
0 
1
ch2_stdi_intlcd, Addr 44 (CP), Address 0x49[6] (Read Only)
This readback displays interlaced versus progressive mode detected by sync channel 2 STDI. The readback is valid if ch2_stdi_dvalid is
set to 1.
Function
ch2_stdi_intlcd
0 
1

9.7.3.3 STDI Usage

Figure 94 shows a flowchart of the intended usage of the STDI block.
Set CHX_STDI_CONT to 0
Set CHX_TRIG_STDI to 0=>1
(positive transition on bit)
to start the STDI state

9.7.3.4 STDI Readback Values for SD, PR, and HD

Standard
720p SMPTE 296M
1125i SMPTE 274M
525p BT 1358
625p BT 1358
1250i BT 709/SMPTE 295
1125i SMPTE 274M 6
1125p SMPTE 274M 10
525i SD
625i SD
Rev. A May 2012
Description
Indicates video signal on sync channel 1 with non interlaced timing
Indicates signal on sync channel 1 with interlaced timing
Description
Indicates video signal on sync channel 2 with non interlaced timing
Indicates signal on sync channel 2 with interlaced timing
No
machine
Low
CHX_BL[13:0], CHX_LCVS[4:0],
CHX_LCF[10:0] and CHX_FCL[12:0]
video standard and programs

Table 53: STDI Readback Values for SD, PR, and HD

CHx_BL[13:0]
27 MHz XTAL
4800
6400
6855
6912
6912
7679
800
13728
13824
Continuous
Mode?
STDI Block
examines input
(flags this by setting
CHX_STDI_DVALID to 0)
Read and
CHX_STDI_DVALI
High
End application reads
video detection results
End application determines
prim_mode and VID_STD
accordingly

Figure 94: STDI Usage Flowchart

CHx_LCF[10:0]
750
562 to 563
525
625
625
562 to 563
1125
262 to 263
312 to 313
277
Yes
Set CHX_STDI_CONT to 1
STDI state machine will run
continuously
Where CHX is CH1 for channel 1
or CHX is CH2 for channel 2
Software function of system controller
Decoder hardware function
CHx_LCVS[4:0] FCL[12:0]
27 MHz XTAL
4 to 5 1761
4 to 5 1761
5 to 6 1761
4 to 5 2109
1 4218
4 to 5 1761
4 to 5 1761
3 1761
2 to 3 2109
ADV7850