Edid/Hdcp Controller Status; Edid/Hdcp Controller Error Codes; Table 86: Hdmi Tx Interrupt Bits In Hdmi Tx Main Map Register 0X96; Table 87: Hdmi Tx Interrupt Bits In Main Map Register 0X97 - Analog Devices ADV7850 Hardware Manual

Bit Name
hdcp_controller_stage_4
edid_ready_interrupt
vsync_interrupt
rx_sense_interrupt
hpd_interrupt
Bit Name
bksv_flag
hdcp_error_interrupt
Bit Name
hpd_state
rx_sense

13.9 EDID/HDCP CONTROLLER STATUS

The Tx core features an EDID/HDCP controller that handles EDID extraction from the downstream sink. This EDID/HDCP controller
also handles HDCP authentication with the downstream sink. The tasks that the Tx EDID/HDCP controller performs are described in
Section 13.13 and Section 13.14.
The current state of the Tx EDID/HDCP controller can be read from the
hdcp_controller_state[3:0], Addr B8 (Main), Address 0xC8[3:0] (Read Only)
This readback indicates the HDCP controller status.
Function
hdcp_controller_state[3
:0]
0000 
0001
0010
0011
0100
0101

13.10 EDID/HDCP CONTROLLER ERROR CODES

If an HDCP authentication occurs between the ADV7850 and the downstream sink, the ADV7850 can trigger an interrupt to notify this
error to the user or the controlling CPU. The EDID/HDCP controller will then report the HDCP error code via the
Rev. A May 2012

Table 86: HDMI Tx Interrupt Bits in HDMI Tx Main Map Register 0x96

Bit Position Description
1 (Second LSB) When set to 1, indicates the HDCP/EDID state machine has
transitioned from state 3 to state 4. Once set, it remains high until
cleared by setting it to 0.
2 When set to 1, indicates the EDID was read from receiver and is
available in Packet Map. Once set, it remains high until cleared by
setting it to 0.
5 When set to 1, indicates that a leading edge on the VSync input to
the Tx core detected. Once set, it remains high until cleared by
setting it to 0.
6 When set to 1, indicates the TMDS clock lines voltage has crossed
1.8 V from high to low or low to high. Once set, remains high until
cleared by setting it to 0.
7 When set to 1, indicates that a transition for high to low or low to
high detected on input HPD signal. Once set, remains high until
cleared by setting it to 0.

Table 87: HDMI Tx Interrupt Bits in Main Map Register 0x97

Bit Position Description
6 When set to 1, indicates KSVs from downstream sink read and
available in Memory Map. Once set, remains high until cleared by
setting it to 0.
7 When set to 1, indicates HDCP/EDID controller reported an error.
This error is available in HDCP_CONTROLLER_ERROR. Once set, it
remains high until cleared by setting it to 0.

Table 88: Status Bits in Main Map Register 0x42

Bit Position
6
5
Description
In reset (no hot plug detected)
Reading EDID
Idle (waiting for HDCP requested)
Initializing HDCP
HDCP enable
Initializing HDCP repeater
Description
See the description on page
See the description on page
hdcp_controller_state[3:0]
355
350
350
status field.
ADV7850