Analog Devices ADV8005 Manuals

Manuals and User Guides for Analog Devices ADV8005. We have 1 Analog Devices ADV8005 manual available for free PDF download: Hardware Reference Manual

Analog Devices ADV8005 Hardware Reference Manual

Analog Devices ADV8005 Hardware Reference Manual (317 pages)

video signal processor

Brand: Analog Devices | Category: Signal Processors | Size: 4 MB

Table of Contents

Table of Contents
2
Understanding the ADV8005 Hardware Manual

10
- Description of the Hardware Manual
  10
- Disclaimer
  10
- Trademark and Service Mark Notice
  10
- Number Notations
  10
- Register Access Conventions
  10
- Acronyms and Abbreviations
  10
- Field Function Description
  13
- References
  14
1 Introduction to the ADV8005

15
- Overview
  15
  - Digital Video Input
    16
  - Flexible Digital Core
    17
  - Video Signal Processor
    17
  - Bitmap on Screen Display
    18
  - External DDR2 Memory
    19
  - HDMI Transmitter
    19
  - Video Encoder
    19
  - Digital Video Output
    19
- Main Features of the ADV8005
  20
  - Video Signal Processor
    20
    
    Primary VSP
    20
    
    Horizontal Pre-Scaler
    20
    
    Secondary VSP
    20
  - Osd
    20
  - Video Encoder
    21
  - HDMI 1.4 Transmitter
    21
  - Additional Features
    21
- Protocol for Main I 2 C Port
  23
- Configuring the ADV8005
  24
2 ADV8005 Top Level Control

25
- ADV8005 Modes of Operation
  26
  - Selecting a Mode
    27
  - Mode 1
    28
  - Mode 2
    29
  - Mode 3
    30
  - Mode 4
    31
  - Mode 5
    32
  - Mode 6
    33
  - Mode 7
    34
  - Mode 8
    35
  - Mode 9 - Bypass
    36
  - Mode 10 - Picture in Picture (Pip) (External OSD Less than 720P)
    37
  - Mode 11 - PIP (External OSD Greater than or Equal to 720P)
    38
  - Mode 12 - Dual Zone OSD
    39
  - Mode 13 - OSD from HDMI RX
    40
  - Mode 14 - Handling Triple Inputs
    41
- ADV8005 Top Level Overview
  41
  - Video Muxing
    41
  - Digital Video Input
    45
    
    Video TTL Input
    46
    
    EXOSD TTL Input
    46
    
    TTL Output
    46
    
    Treatment O F Unused TTL Inputs
    48
    
    Serial Video Rx
    52
    
    Primary Input Channel
    52
    
    Secondary Input Channel
    57
    
    RX Input Channel
    61
  - Updither Configuration
    62
  - Clock Configuration
    62
    
    PVSP Output Timing
    66
    
    SVSP Output Timing
    67
    
    Frame Tracking
    67
  - DDR2 Interface
    68
    
    DDR2 Configuration
    69
    
    DDR2 Bandwidth and Memory Selection
    70
    
    Single DDR2 Memory Configuration
    72
    
    DDR2 Loopback Test
    72
  - I 2 C Auto Increment
    73
  - SPI Loop through
    74
  - VBI Data Insertion
    74
    
    Extraction Overview
    74
    
    Ancillary Data Extraction
    74
    
    SPI Data Extraction
    75
    
    VBI Data Delay
    75
  - Resets
    76
  - Image Processing Colorimetry Breakdown
    78
  - AV-Codes
    79
  - Color Space Conversion
    83
    
    Primary Input Channel CSC
    83
    
    Secondary Input Channel CSC
    86
    
    RX Input Channel CSC
    89
    
    TTL Output CSC
    92
    
    HDMI Transmitter Cscs
    95
  - VGA Position and Phase Information
    98
  - ADV8005 Silicon Revision
    103
  - System Configuration
    103
3 Video Signal Processing

104
- Introduction
  104
- Primary VSP
  104
  - Introduction to PVSP
    104
    
    Autoconfiguration
    105
    
    Customized Input/Output Video Format Configuration
    107
    
    Field/Frame Buffer Number
    108
    
    Field/Frame Buffer Address and Size
    108
    
    Frame Latency
    110
    
    Game Mode
    111
    
    Low Latency Mode
    112
    
    Freezing Output Video
    113
    
    Progressive Cadence Detection
    113
  - PVSP Video Input Module
    114
    
    VIM Cropper
    114
    
    Horizontal down Scaler
    116
    
    Scaler Interpolation Mode
    116
    
    Scaler Controls
    117
    
    Pixel Packer
    117
  - PVSP Video Output Module
    118
    
    Pixel Unpacker
    119
    
    VOM Cropper
    119
    
    Motion Detection
    120
    
    Low Angle De-Interlacing
    121
    
    Cadence Detection
    121
    
    CUE Correction
    122
    
    Random Noise Reduction
    123
    
    Mosquito Noise Reduction
    124
    
    Block Noise Reduction
    124
    
    Sharpness Enhancement
    126
    
    Scaler
    126
    
    Panorama Mode
    128
    
    Output Port
    128
    
    Demo Function
    131
    
    Progressive to Interlaced Converter
    133
    
    Automatic Contrast Enhancement
    134
- Secondary VSP
  134
  - Introduction to SVSP
    134
    
    Autoconfiguration
    136
    
    Customized Input/Output Video Format Configuration
    138
    
    Frame Buffer Number
    138
    
    Frame Buffer Address and Size
    138
    
    Frame Latency
    140
    
    Freezing Output Video
    141
  - SVSP Video Input Module (VIM)
    141
    
    VIM Cropper
    142
    
    Scaler
    143
    
    Scaler Interpolation Mode
    144
    
    VIM Miscellaneous Control
    144
    
    Panorama Mode
    145
    
    Pixel Packer
    145
  - SVSP Video Output Module
    146
    
    Pixel Unpacker
    147
    
    VOM Cropper
    147
    
    Output Port
    148
    
    DDR Bypass Mode
    151
    
    Progressive to Interlaced Converter in SVSP
    152
- VSP Register Access Protocols
  152
  - Bootup Protocol
    153
  - Reboot Protocol
    154
  - Gentle Reboot Protocol
    155
  - VOM Set Protocol
    156
  - Free Access Protocol
    156
- Horizontal Pre-Scaler
  157
  - HPS Downscaling
    158
  - HPS Upscaling
    159
  - Using the HPS for Converting between 3D to 2D Video Formats
    160
  - Side by Side Full
    161
  - Side by Side Full
    162
- External Sync Mode
  162
  - Functional Description
    163
- Progressive to Interlaced Conversion
  165
4 On Screen Display

166
- Introduction
  166
  - Features
    166
  - OSD System Application Diagram
    166
  - Typical OSD Component Sizes
    167
- Architecture Overview
  167
  - Introduction
    167
  - Top Level Diagram
    167
  - OSD Blending
    168
  - External Alpha Blending
    169
  - OSD Core
    169
    
    OSD Core Region Definition
    170
    
    OSD Color Space
    171
  - OSD Timers
    171
  - OSD Scaler
    174
  - OSD Master/Slave SPI Interface
    174
    
    Overview
    174
    
    SPI Slave Interface
    178
    
    SPI Master Interface
    180
  - OSD Initialization
    181
5 Serial Video Receiver

182
- Detect
  182
- TMDS Clock Activity Detection
  183
- Clock and Data Termination Control
  183
- AV Mute Status
  184
- Deep Color Mode Support
  184
- Video FIFO
  185
- Pixel Repetition
  186
- Sync Signal Polarity Readbacks
  187
- Infoframe Registers
  188
  - Infoframe Collection Mode
    188
  - Infoframe Checksum Error Flags
    188
  - AVI Infoframe Registers
    189
  - SPD Infoframe Registers
    190
  - MPEG Source Infoframe Registers
    191
  - Vendor Specific Infoframe Registers
    191
- Packet Registers
  192
  - ISRC Packet Registers
    192
  - Gamut Metadata Packets
    194
- Customizing Packet/Infoframe Storage Registers
  195
- HDMI Section Reset Strategy
  196
6 HDMI Transmitter

197
- General Controls
  197
- Reset Strategy
  199
- HDMI DVI Selection
  199
- AV Mute
  199
- Source Product Description Infoframe
  200
- Spare Packets and VSI Support
  201
- System Monitoring
  204
  - General Status and Interrupts
    204
  - VSYNC Interrupt
    205
- EDID/HDCP Controller Status
  205
- EDID/HDCP Controller Error Codes
  205
- Video Setup
  206
  - Input Format
    206
  - Video Mode Detection
    206
  - Pixel Repetition
    207
  - Video Related Packets and Infoframes
    208
  - AVI Infoframe
    208
  - MPEG Infoframe
    209
  - Gamut Metadata
    210
- Audio Setup
  212
  - Audio Architecture
    212
  - Audio from Serial Video Rx
    212
  - Audio Configuration
    213
    
    I2S Audio
    215
    
    SPDIF Audio
    221
    
    DSD Audio
    221
    
    HBR Audio
    222
  - N and CTS Parameters
    223
    
    N Parameter
    223
    
    CTS Parameter
    224
    
    Recommended N and Expected CTS Values
    224
  - Audio Sample Packets
    225
  - Audio Infoframe
    230
  - ACP Packet
    230
  - ISRC Packet
    231
- EDID Handling
  233
  - Reading the EDID
    233
  - EDID Definitions
    233
  - Additional Segments
    233
  - Edid_Tries Control
    234
  - EDID Reread Control
    234
- HDCP Handling
  235
  - One Sink and no Upstream Devices
    235
  - Multiple Sinks and no Upstream Devices
    236
  - Software Implementation
    238
  - AV Mute
    239
- Audio Return Channel
  239
- Charge Injection Settings
  240
- Enabling and Disabling the HDMI TMDS Otuputs
  240
- HDMI TX Source Termination
  241
- HDMI ACR Packet Transmission
  242
7 Video Encoder Introduction to the ADV8005

243
- Introduction
  243
- Input Configuration
  243
- Output Configuration
  246
- Additional Design Features
  247
  - Output Oversampling
    248
  - Subcarrier Frequency Lock (SFL) Mode
    248
  - SD VCR FF/RW Synchronization
    249
  - Vertical Blanking Interval
    249
  - SD Subcarrier Frequency Control
    249
    
    Programming the FSC
    250
  - SD Non Interlaced Mode (240P/288P)
    250
  - Filters
    250
    
    SD Filters
    250
    
    ED/HD Filters
    253
  - ED/HD Test Pattern Generator
    254
  - Color Space Conversion Matrix
    255
  - ED/HD Manual CSC Matrix Adjust Feature
    255
    
    Programming the CSC Matrix
    257
  - SD Luma and Color Scale Control
    257
  - SD Hue Adjust Control
    258
  - SD Brightness Detect
    259
  - SD Brightness Control
    259
  - Double Buffering
    260
    
    ED/HD Doubling Buffering
    260
    
    SD Doubling Buffering
    260
  - Programmable DAC Gain Control
    261
  - Gamma Correction
    262
    
    ED/HD Gamma Correction
    264
    
    SD Gamma Correction
    265
  - ED/HD Sharpness Filter and Adaptive Filter Controls
    266
    
    ED/HD Sharpness Filter Mode
    266
    
    ED/HD Adaptive Filters
    267
    
    ED/HD Adaptive Filter Modes
    268
    
    ED/HD Sharpness Filter and Adaptive Filter Application Examples
    269
  - SD Digital Noise Reduction
    271
    
    Coring Gain Border
    272
    
    Coring Gain Data
    272
    
    DNR Threshold
    273
    
    Border Area
    273
    
    Block Size Control
    273
    
    DNR Input Select Control
    274
    
    DNR Mode Control
    274
    
    DNR Block Offset Control
    275
    
    SD Active Video Edge Control
    275
- Vertical Blanking Interval
  276
- DAC Configurations
  277
  - Voltage Reference
    277
  - Video Output Buffer and Optional Output Filter
    277
8 Interrupts

280
- Interrupt Pins
  280
  - Interrupt Duration
    280
  - Storing Masked Interrupts
    281
- Serial Video Rx Interrupts
  281
  - Introduction
    281
  - Interrupt Architecture Overview
    284
    
    Multiple Interrupt Events
    285
  - Serial Video Interrupts Validity Checking Process
    285
- VSP and OSD Section
  285
  - Interrupt Architecture Overview
    286
- HDMI Tx Core
  286
  - Introduction
    286
  - Interrupt Architecture Overview
    287
  - HDMI Tx Interrupt Polarity
    287
- PCB Layout Recommendations
  288
  - Analogue/Digital Video Interface Outputs
    288
  - External DDR2 Memory Requirements
    288
Appendix A

288
- Power Supply Bypassing
  289
- General Digital Inputs and Outputs
  289
- XTAL and Load Cap Value Selection
  289
- Encoder Component Placement
  290
- HDMI Transmitter Component Placement
  290
- Power Supply Design and Sequencing
  290
- Unused Pin List
  292
Appendix B

292
- Pixel Input and Output Formats
  304
Appendix C

304

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