Readback Registers; User Interface Fori; Registers; Vdp Register Readback Protocols - Analog Devices ADV7850 Hardware Manual

10.4

READBACK REGISTERS

I 2 C readback registers have separate registers for CCAP, CGMS, WSS, Gemstar, VPS, PDC/UTC, and VITC. The details of these registers
and their access procedure are described in Section 10.5.
10.5 USER INTERFACE FOR I
VDP supports two types of I
• Dedicated I C registers (normal I
2
•
Shared I 2 C (fast I
Dedicated I C readback registers have separate registers for CCAP, CGMS, WSS, GEMSTAR, VPS, PDC/UTC, and VITC, whereas the fast
2
I C space has a shared space of 45 registers that can be used for any or a combination of VBI data standards. The details of these registers
2
and their access procedure are described in this section.

VDP Register Readback Protocols

10.5.1

10.5.1.1 Data Available Updates

The VDP decodes all enabled VBI data standards in real time. Since the I
possible that when the registers are accessed, they are updated with data from the next line. In order to avoid this, the VDP block has a
clear control bit and an available status bit accompanying all the VDP readback registers.
Initially, the user has to clear the I
available bit to low and indicates that the data in the associated readback registers are not valid. After the VDP decodes the next line of the
corresponding VBI data, the decoded data is placed in the I
data is now available.
Though the VDP will decode this VBI data, if present, in subsequent lines, the decoded data will not be updated to the readback registers
until the CLEAR bit is set HIGH again. However, this data will be available through the 656 ancillary data packets.
Example I C Readback Procedure:
2
The following tasks are performed to read one packet (line) of PDC data from the decoder.
1. Write '10' to gs_vps_pdc_utc_cgmstb[2:0]
2. Set status_clear_gems_vps to 1 to enable the update of I
3. Poll the vdp_status_gs_vps_pdc_utc_cgmstb / gs_pdc_vps_utc_avl_st bit going high to check the availability of the PDC
packets.
4. Read the data bytes from the PDC I
5. Repeat steps 1 to 4 to read another line or packet of data.
6. To read a packet of CC, CGMS, or WSS, steps 2, 3, and 4 only are required since they have dedicated registers.
Rev. A May 2012
CGMS Type B Readback Registers VDP Map
vdp_gs_vps_pdc_utc_cgmstb_data[31:24]
vdp_gs_vps_pdc_utc_cgmstb_data[39:32]
vdp_gs_vps_pdc_utc_cgmstb_data[47:40]
vdp_gs_vps_pdc_utc_cgmstb_data[55:48]
vdp_gs_vps_pdc_utc_cgmstb_data[63:56]
vdp_gs_vps_pdc_utc_cgmstb_data[71:64]
vdp_gs_vps_pdc_utc_cgmstb_data[79:72]
vdp_gs_vps_pdc_utc_cgmstb_data[87:80]
vdp_gs_vps_pdc_utc_cgmstb_data[95:88]
vdp_gs_vps_pdc_utc_cgmstb_data[103:96]
C READBACK REGISTERS
2
C interfaces for the readback of decoded data:
2
C bus)
2
2 C bus)
C readback register by writing 1 to the clear bit (this control is self clearing). This resets the state of the
2
to specify that PDC data has to be updated to I
C registers.
2
C access speed is much lower than the decoded rate, it is
2
C readback register and the available bit is set to high to indicate that valid
2
C registers.
2
320
Address
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
C registers.
2
ADV7850