Analog Devices ADV7610 Hardware User's Manual
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Analog Devices ADV7610 Hardware User's Manual

Analog Devices ADV7610 Hardware User's Manual

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Advantiv

SCOPE

This user guide provides a detailed description of the Advantiv®

DISCLAIMER

Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use.
Specifications are subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

FUNCTIONAL BLOCK DIAGRAM

XTALP
DPLL
XTALN
SCL
SDA
CEC
CEC
CONTROLLER
5V DETECT
RXA_5V
AND HPD
HPA_A/INT2*
CONTROLLER
EDID
DDCA_SDA
REPEATER
DDCA_SCL
CONTROLLER
RXA_C±
PLL
RXA_0±
EQUALIZER
RXA_1±
RXA_2±
*INT2 CAN BE ONLY OUTPUT ON ONE OF THE PINS: SCLK/INT2, MCLK/INT2, OR HPA_A/INT2.
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.
ADV7610
HDMI Receiver Functionality and Features
CONTROL
INTERFACE
2
I
C
CONTROL
AND DATA
HDCP
EEPROM
HDCP
EQUALIZER
ENGINE
Rev. 0 | Page 1 of 184
ADV7610
HDMI® receiver functionality and features.
BACKEND
COLOR SPACE
CONVERSION
HDMI
PROCESSOR
COMPONENT
PROCESSOR
A
DATA
B
PREPROCESSOR
C
AND COLOR
SPACE
CONVERSION
PACKET/
INFOFRAME
MEMORY
PACKET
PROCESSOR
Figure 1.
Hardware User Guide
12
12
12
INTERRUPT
CONTROLLER
(INT1, INT2)
MUTE
AUDIO
PROCESSOR
ADV7610
UG-438
P0 TO P7
P8 TO P15
P16 TO P23
LLC
HS
VS/FIELD/ALSB
DE
INT1
INT2*
I2S0 TO I2S3
LRCLK
SCLK/INT2*
MCLK/INT2*

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Summary of Contents for Analog Devices ADV7610

  • Page 1: Scope

    DISCLAIMER Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use.

  • Page 2: Table Of Contents

    Functional Block Diagram .............. 1 Deep Color Mode Support ............34 Revision History ................3 Video FIFO .................. 34 Using the ADV7610 Hardware User Guide ........4 Pixel Repetition ................36 Number Notations ................ 4 HDCP Support ................37 Register Access Conventions ............4 HDMI Synchronization Parameters ........

  • Page 3: Revision History

    Hardware User Guide UG-438 Free Run Mode ................. 134 Register Access and Serial Ports Description ......174 CP Status ................... 138 Main I C Port ................174 CP Core Bypassing ..............138 DDC Ports .................. 177 Consumer Electronics Control ........... 139 Appendix A ..................

  • Page 4: Using The Adv7610 Hardware User Guide

    UG-438 Hardware User Guide USING THE ADV7610 HARDWARE USER GUIDE NUMBER NOTATIONS Table 1. Notation Description Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0.
  • Page 5 Hardware User Guide UG-438 Acronym/Abbreviation Description Key selection vector. Line locked clock. Least significant bit. L-PCM Linear pulse coded modulated. Mbps Megabit per second. MPEG Moving picture expert group. Millisecond. Most significant bit. No connect. One-time programmable. Pj’ HDCP enhanced link verification response. Refer to digital content protection documentation in the References section. Ri’...

  • Page 6: Field Function Descriptions

    UG-438 Hardware User Guide FIELD FUNCTION DESCRIPTIONS Throughout this user guide, a series of function tables are provided. The function of a field is described in a table preceded by the bit name, a short function description, the I C map, the register location within the I C map, and a detailed description of the field.

  • Page 7: Introduction To The Adv7610

    HDMI stream. HDMI audio formats, including super audio CD (SACD) via direct stream digital (DSD and high bit rate (HBR) are supported by the ADV7610. The HDMI receiver has advanced audio functionality, such as a mute controller, that prevents audible extraneous noise in the audio output.
  • Page 8 UG-438 Hardware User Guide Video Output Formats • Double data rate (DDR) 8-/12-bit 4:2:2 YCrCb • DDR supported only up to 50 MHz (an equivalent to data rate clocked with 100 MHz clock in SDR mode) • Pseudo DDR (CCIR-656 type stream) 8-/12-bit 4:2:2 YCrCb for 525i, 625i, 525P, and 625P •...

  • Page 9: Pin Configuration And Function Descriptions

    Hardware User Guide UG-438 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS HPA_A/ MCLK/ SCLK/ RXA_5V DDCA_SCL PVDD XTALN XTALP INT1 DVDD INT2 INT2 INT2 TVDD TVDD DDCA_SDA RESET DVDD LRCLK RXA_C– RXA_C+ I2S1 I2S3 RXA_0+ RXA_0– DVDD I2S0 I2S2 FIELD/ RXA_1+ RXA_1– DVDD ALSB RXA_2+...
  • Page 10 ADV7610 circuitry. XTALP Miscellaneous Input Pin for a 28.63636 MHz Crystal, or an External 1.8 V, 28.63636 MHz Clock analog Oscillator Source to Clock the ADV7610. XTALN Miscellaneous Crystal Input. Input pin for 28.63636 MHz crystal. analog Digital input/output Consumer Electronic Control Channel.

  • Page 11: Global Control Registers

    UG-438 GLOBAL CONTROL REGISTERS The register control bits described in this section deal with the general control of the chip, and the CP and the HDMI receiver sections of the ADV7610. ADV7610 REVISION IDENTIFICATION RD_INFO[15:0], IO, Address 0xEA[7:0]; Address 0xEB[7:0] (Read Only) Chip revision code.
  • Page 12 Powers down CP and digital section of HDMI block Power-Down Modes ADV7610 supports the following power-down modes: • Power-Down Mode 0 • Power-Down Mode 1 Table 5 shows the power-down and normal modes of ADV7610. Table 5. Power-Down Modes POWER_DOWN Bit CEC_POWER_UP Bit EDID Power-Down Mode Disabled Enabled...

  • Page 13: Global Pin Control

    5 ms. It is recommended to wait 5 ms after the low pulse before an I C write is performed to the ADV7610. Reset Controls...
  • Page 14 VS/FIELD/ALSB • • The drive strength controls for these signals are provided via the DR_STR_SYNC bits. The ADV7610 does not support tristating via a dedicated pin. TRI_SYNCS, IO, Address 0x15[3] Synchronization output pins tristate control. The synchronization pins under this control are HS, VS/FIELD/ALSB, and DE.
  • Page 15 Hardware User Guide UG-438 Drive Strength Selection DR_STR It may be desirable to strengthen or weaken the drive strength of the output drivers for electromagnetic compatibility (EMC) and crosstalk reasons. This section describes the controls to adjust the output drivers used by the CP and HDMI modes. The drive strength DR_STR_SYNC[1:0] bits allow the user to select the strength of the following synchronization signals: •...
  • Page 16 Changing the polarity of the LLC clock output may be necessary in order to meet the setup and hold time expectations of the downstream devices processing the output data of the ADV7610. It is expected that these parameters must be matched regardless of the type of video data that is transmitted.
  • Page 17 Hardware User Guide UG-438 Digital Synthesizer Controls ADV7610 features two digital encoder synthesizers that generate the following clocks: • Video DPLL: this clock synthesizer generates the pixel clock. It undoes the effect of deep color and pixel repetition that are inherent to HDMI streams.

  • Page 18: Primary Mode And Video Standard

    PRIMARY MODE AND VIDEO STANDARD Setting the primary mode and choosing a video standard are the most fundamental settings when configuring the ADV7610. There are two primary modes for the ADV7610: HDMI-component and HDMI-graphic modes. The appropriate mode should be set with PRIM_MODE[3:0].
  • Page 19 Hardware User Guide UG-438 PRIM_MODE[3:0] VID_STD[5:0] Code Description Processor Code Input Video Output Resolution Comment 0101 HDMI-COMP 000000 SD 1×1 525i 720 × 480 HDMI receiver support (Component video) 000001 SD 1×1 625i 720 × 576 000010 SD 2×1 525i 720 ×...

  • Page 20: Hdmi Decimation Modes

    Set PRIM_MODE to 0x5 and VID_STD to 0x19 Note: Decimating the video data from an HDMI stream is optional and should be performed only if it is required by the downstream devices connected to the ADV7610. PRIMARY MODE AND VIDEO STANDARD CONFIGURATION FOR HDMI FREE RUN...

  • Page 21: Recommended Settings For Hdmi Inputs

    Hardware User Guide UG-438 RECOMMENDED SETTINGS FOR HDMI INPUTS This section provides the recommended settings for an HDMI input encapsulating a video resolution corresponding to a selection Video ID Code described in the 861 specification. Table 7 provides the recommended settings for the following registers: •...
  • Page 22 UG-438 Hardware User Guide Recommended Settings Recommended Settings if Free Run Not Used Video ID Codes Pixel if Free Run Used and or Free Run Used and (861 Specification) Formats Repetition DIS_AUTO_PARAM_BUFF = 0 DIS_AUTO_PARAM_BUFF = 1 Not applicable SVGA 800 × 600p @ 56 PRIM_MODE = 0x6 PRIM_MODE = 0x6 VID_STD = 0x0...

  • Page 23: Pixel Port Configuration

    Refer to the DLL settings for 656, 8-/10-/12-bit modes in the DLL on LLC Clock Path section. Bus Rotation and Reordering Controls Bus reordering controls are available for ADV7610. OP_CH_SEL[2:0] allows the three output buses to be rearranged, thus providing six different output possibilities.

  • Page 24: Llc Controls

    Note: It has no effect for 24-bit SDR modes and DDR modes. LLC CONTROLS ADV7610 has a limited number of adjustment features available for the line locked clock (LLC) output. The polarity of the LLC can be inverted and the LLC of the output driver can be tristated. Controls also exist to skew the LLC versus the output data to achieve suitable setup and hold times for any back end device.
  • Page 25 Hardware User Guide UG-438 LLC_DLL_PHASE[4:0], IO, Address 0x19[4:0] A control to adjust LLC DLL phase in increments of 1/32 of a clock period. Function LLC_DLL_PHASE[4:0] Description 00000 (default) Default xxxxx Sets one of 32 phases of DLL to vary LLC CLK DLL Settings for 656, 8-/10-/12-Bit Modes The following table shows the settings that must be used to enable 8-/10-/12-bit, 656 output.

  • Page 26: Hdmi Receiver

    Figure 3. Functional Block Diagram of HDMI Core +5 V CABLE DETECT The HDMI receiver in the ADV7610 can monitor the level on the +5 V power signal pin of the HDMI port. The results of this detection can be read back from the following I C registers.

  • Page 27: Hot Plug Assert

    Does not use 5 V input pins as reset signal for HDMI section HOT PLUG ASSERT ADV7610 features hot plug assert (HPA) control for its HDMI port. The purpose of the control and its corresponding output pin is to communicate to an HDMI transmitter that it is possible to access the enhanced-extended display identification (E-EDID) connected to the DDC bus.
  • Page 28 UG-438 Hardware User Guide HPA_AUTO_INT_EDID[1:0], Addr 68 (HDMI), Address 0x6C[2:1] This control selects the type of automatic control on the HPA output pins. This bit has no effect when HPA_MANUAL is set to 1. Function HPA_AUTO_INT_EDID[1:0] Description HPA of an HDMI port asserted high immediately after internal EDID activated for that port. HPA of a specific HDMI port deasserted low immediately after internal E-EDID is de-activated for that port.

  • Page 29: E-Edid/Repeater Controller

    DDC port, even when the part is powered down (refer to the Power-Down Modes section). These HDMI transmitters can then read the capabilities of the powered-down application integrating the ADV7610 by accessing its internal E-EDID through the DDC ports.

  • Page 30: Transitioning Of Power Modes

    The internal E-EDID can be read by current address read sequences on the DDC port. • ADV7610 supports the segment pointer, which is set at Register Address 0x60 through the DDC bus, and used in combination with the internal E-EDID address (0xA0) to access the internal E-EDID.

  • Page 31: Tmds Equalization

    • After EDID_A_ENABLE is set to 1, the ADV7610 EDID/repeater controller computes the checksums and updates the internal RAM address locations 0x7F, 0xFF, 0X17F, and 0x1FF in the internal EDID RAM with the computed checksums. • After power up, the ADV7610 E-EDID controller sets all bytes in the internal EDID RAM to 0, this operation takes less than 1 ms.

  • Page 32: Hdmi/Dvi Status Bits

    The clock detection flags is valid, irrespective of the mode the part is set into via the PRIM_MODE[3:0] register. Clock and Data Termination Control ADV7610 provides controls for the TMDS clock and data termination on the HDMI port. Note: The clock termination of the port by HDMI_PORT_SELECT[2:0] must always be enabled.

  • Page 33: Tmds Measurement

    VIDEO_3D_RAW Description Video 3D not detected (read only) Video 3D detected TMDS MEASUREMENT ADV7610 contains logic that measures the frequency of the TMDS clock transmitted. The TMDS frequency can be read back via the TMDSFREQ[8:0] and TMDSFREQ_FRAC[6:0] registers. TMDS Measurement after TMDS PLL The TMDSFREQ measurement is provided by a clock measurement circuit located after the TMDS PLL.

  • Page 34: Deep Color Mode Support

    Tolerance in MHz for new TMDS frequency detection DEEP COLOR MODE SUPPORT The Deep Color mode information that the ADV7610 extracts from the general control packet can be read back from DEEP_COLOR_MODE[1:0]. DEEP_COLOR_MODE[1:0], Addr 68 (HDMI), Address 0x0B[7:6] (Read Only)
  • Page 35 Hardware User Guide UG-438 TMDS TMDS CLOCK DPLL DIVIDER TMDS CH0 TMDS CHANNEL 0 TMDS SAMPLING TMDS CH1 TMDS FIFO TMDS DECODING DATA CHANNEL 1 RECOVERY TMDS CH2 TMDS CHANNEL 2 Figure 5. HDMI Video FIFO The video FIFO is designed to operate completely autonomously. It automatically resynchronizes the read and write pointers if they are about to point to the same location.

  • Page 36: Pixel Repetition

    In HDMI mode, video formats with TMDS rates below 25 M pixels/sec require pixel repetition in order to be transmitted over the TMDS link. When the ADV7610 receives this type of video format, it discards repeated pixel data automatically, based on the pixel repetition field available in the AVI InfoFrame.

  • Page 37: Hdcp Support

    Hardware User Guide UG-438 DEREP_N_OVERRIDE, Addr 68 (HDMI), Address 0x41[4] This control allows the user to override the pixel repetition factor. The ADV7610 then uses DEREP_N instead of HDMI_PIXEL_REPETITION[3:0] to discard video pixel data from the incoming HDMI stream. Function...
  • Page 38 ADV7610 supports the 1.1_FEATURES, FAST_REAUTHENTICATION, and FAST_I2C speed HDCP features. The BCAPS register must be initialized appropriately if these features are to be supported by the application integrating the ADV7610, for example, set BCAPS[0] to 1 to support FAST_REAUTHENTICATION. •...
  • Page 39 Hardware User Guide UG-438 START (AFTER POWER-UP) HDCP_KEY_READ = 0 HDCP_KEY_ERROR = 0 READ KSV AND CHECKSUM CS1 FROM HDCP OTP ROM DERIVE CHECKSUM CS1' FROM KSV HDCP_KEY_ERROR = 1 CS1 = CS1' SET BKSV (HDCP REGISTER ADDRESS 0x00 BKSV = KSV HDCP_KEY_READ = 1 HDCP_KEY_ERROR = 0 Figure 6.
  • Page 40 After the part has powered up, it is recommended to wait for 1 ms before checking the HDCP_KEYS_READ HDCP_KEY_ERROR flag bits. This ensures that the ADV7610 had sufficient time to access the internal HDCP ROM and set the HDCP_KEYS_READ HDCP_KEY_ERROR flag bits.

  • Page 41: Hdmi Synchronization Parameters

    UG-438 HDMI SYNCHRONIZATION PARAMETERS ADV7610 contains the logic required to measure the details of the incoming video resolution. The HDMI synchronization parameters readback registers from the HDMI Map can be used, in addition to the STDI registers from the CP (refer to the Standard Detection and Identification section), to estimate the video resolution of the incoming HDMI stream.
  • Page 42 UG-438 Hardware User Guide TOTAL_LINE_WIDTH[13:0], Addr 68 (HDMI), Address 0x1E[5:0]; Address 0x1F[7:0] (Read Only) Total line width is a horizontal synchronization measurement. This gives the total number of pixels per line. This measurement is valid only when the DE regeneration filter has locked. Function TOTAL_LINE_WIDTH[13:0] Description...
  • Page 43 The HSync transitions occur on different pixels count for 15 consecutive video lines Vertical Filters and Measurements ADV7610 integrates a HDMI vertical filter, which performs measurements on the VSync of the HDMI stream on the selected port. These measurements are available in the HDMI map and can be used to determine the resolution of the incoming video data stream.
  • Page 44 UG-438 Hardware User Guide FIELD0_TOTAL_HEIGHT[13:0], Addr 68 (HDMI), Address 0x26[5:0]; Address 0x27[7:0] (Read Only) Field 0 total height is a vertical synchronization measurement. This readback gives the total number of half lines in Field 0. This measurement is valid only when the vertical filter has locked. Function FIELD0_TOTAL_HEIGHT[13:0] Description...
  • Page 45 Hardware User Guide UG-438 DATA ENABLE HSYNC VSYNC NOTE: TOTAL NUMBER OF LINES IN FIELD 0. UNIT IS IN HALF LINES. ACTIVES NUMBER OF LINES IN FIELD 0. UNIT IS IN HALF LINES. VSYNC FRONT PORCH WIDTH IN FIELD 0. UNIT IS IN HALF LINES. VSYNC PULSE WIDTH IN FIELD 0.

  • Page 46: Audio Control And Configuration

    VSync comes at a different pixels count for two consecutive frames. AUDIO CONTROL AND CONFIGURATION ADV7610 extracts an L-PCM, IEC 61937 compressed or DST audio data stream from their corresponding audio packets (that is, audio sample or DST) encapsulated inside the HDMI data stream.
  • Page 47 • TMDS PLL is locked (refer to TMDS_PLL_LOCKED) • ADV7610 has received an ACR packet with N and CTS parameters within a valid range The audio DPLL lock status can be monitored via AUDIO_PLL_LOCKED. AUDIO_PLL_LOCKED, Addr 68 (HDMI), Address 0x04[0] (Read Only) A readback to indicate the Audio DPLL lock status.

  • Page 48: Audio Fifo

    UG-438 Hardware User Guide AUDIO FIFO The audio FIFO can store up to 128 audio stereo data from the audio sample or DST packets. Stereo audio data are added into the FIFO from the audio packet received. Stereo audio data are retrieved from the FIFO at a rate corresponding to 128 times the audio sampling frequency, f The status of the audio FIFO can be monitored through the status flags FIFO_UNDERFLO_RAW, FIFO_OVERFLO_RAW, FIFO_NEAR_OVFL_RAW, and FIFO_NEAR_UFLO_RAW.

  • Page 49: Audio Packet Type Flags

    • DST packets The following flags are provided to monitor the type of audio packets received by the ADV7610. Figure 13 shows the algorithm that can be implemented to monitor the type of audio packet processed by the ADV7610. AUDIO_MODE_CHNG_RAW, IO, Address 0x83[5] (Read Only) Status of audio mode change interrupt signal.
  • Page 50 No HBR audio packet received within the last 10 HSync HBR audio packet received within the last 10 HSync Notes • ADV7610 processes only one type of audio packet at a time. • ADV7610 processes the latest type of audio packet that it received.

  • Page 51: Audio Output Interface

    HBR_PACKET_DET? BEING RECEIVED BEING RECEIVED Figure 13. Monitoring Audio Packet Type Processed by ADV7610 AUDIO OUTPUT INTERFACE ADV7610 has a dedicated 3-pin audio output interface. The output pin names and descriptions are shown in Table 9. Table 9. Audio Outputs and Clocks...
  • Page 52 UG-438 Hardware User Guide Table 10 shows the default configurations for the various possible output interfaces. Table 10. Default Audio Output Pixel Port Mapping Output Pixel Port S /SPDIF Interface I2S0 S 0/SDPIF0 I2S1 S 1/SDPIF1 I2S2 S 2/SDPIF2 I2S3 S 3/SDPIF3 Note: It is possible to tristate the audio pins using the global controls, as described in the Tristate Audio Output Drivers section.
  • Page 53 Hardware User Guide UG-438 Notes • I2SOUTMODE is effective when the ADV7610 is configured to output I S streams or AES3 streams. This is the case in the situation where the ADV7610 receives audio sample packets • ADV7610 receives HBR packets, OVR_MUX_HBR is set to 1, and MUX_HBR_OUT is set to 2’b00, 2’b01, 2’b10 or 2’b11.
  • Page 54 UG-438 Hardware User Guide LEFT RIGHT MSB – 1 MSB – 1 MSB EXTENDED MSB EXTENDED 32 CLOCK SLOTS 32 CLOCK SLOTS Figure 15. Timing Audio Data Output in Right Justified Mode LEFT RIGHT 32 CLOCK SLOTS 32 CLOCK SLOTS Figure 16.
  • Page 55 Figure 19. AES3 Stream Timing Diagram DSD Audio Interface and Output Controls ADV7610 incorporates a four DSD channel interface used to output the audio stream extracted from DSD packets. Each of the DSD channels carries an oversampled 1-bit representation of the audio signal as delivered on SACDs.
  • Page 56 Override by outputting DSD/DST data HBR Interface and Output Controls ADV7610 can receive HBR audio stream packets. The ADV7610 outputs HBR data over four of the audio output pins in any of the following formats: • An SDPIF stream conforming to the IEC60958 specification (refer to Figure 17). The following configuration is required to output an SPDIF stream on the HBR output pins: •...

  • Page 57: Mclkout Setting

    Hardware User Guide UG-438 OVR_MUX_HBR, Addr 68 (HDMI), Address 0x01[2] A control to select automatic or manual configuration for HBR outputs. Automatically, HBR outputs are encoded as SPDIF streams. In manual mode, MUX_HBR_OUT selects the audio output interface. Function OVR_MUX_HBR Description 0 (default) Automatic HBR output control...

  • Page 58: Audio Muting

    UG-438 Hardware User Guide AUDIO MUTING ADV7610 integrates an advanced audio mute function that is designed to remove all extraneous noise and pops from a 2-channel L-PCM audio stream at sample frequencies up to 48 kHz. The hardware for audio mute function is composed of the following three blocks: •...
  • Page 59 Both Table 8 and Table 14 provide a column with the heading ‘Corresponding Status Register(s)’ . This column lists the status registers that convey information related to their corresponding audio mute masks or coast masks. • ADV7610 mute works differently for compressed audio data. In the case of compressed audio, mute outputs a constant stream of 0. •...
  • Page 60 UG-438 Hardware User Guide Table 14. Selectable Mute Conditions HDMI Map Corresponding Status Bit Name Address Description Register(s) MT_MSK_COMPRS_AUD 0x14[5] Causes audio mute if audio is compressed CS_DATA[1] MT_MSK_AUD_MODE_CHNG 0x14[4] Causes audio mute if audio mode changes between AUDIO_SAMPLE_PCKT_DET PCM, DSD, DST, or HBR formats MT_MSK_PARITY_ERR 0x14[1] Causes audio mute if parity bits in audio samples are...
  • Page 61 0 (default) AVMUTE not set AVMUTE set Audio Mute Signal ADV7610 can output an audio mute signal that can be used to control the muting in a back end audio device processing the audio data output by the ADV7610 (for example, DSP).

  • Page 62: Audio Clock Regeneration Parameters

    UG-438 Hardware User Guide Audio Stream with Incorrect Parity Error ADV7610 discards audio sample packets that have an incorrect parity bit. When these samples are received, the ADV7610 repeats the previous audio sample with a valid parity bit. The audio stream out of the...

  • Page 63: Channel Status

    Hardware User Guide UG-438 CHANGE_N_RAW, IO, Address 0x7E[3] (Read Only) Status of the ACR N Value changed interrupt signal. When set to 1 it indicates the N Value of the ACR packets has changed. Once set, this bit will remain high until it is cleared via CHANGE_N_CLR. Function CHANGE_N_RAW Description...
  • Page 64 UG-438 Hardware User Guide START ENABLE THE CS_DATA_VALID_ST INITIALIZATION INTERRUPT CS_DATA_VALID_S T SET TO 1? CHECK IF THE CS_DATA_VALID SET CS_DATA_VALID_CLR TO 1 INTERRUPT HAS TRIGGERED CS_DATA_VALID_R AW SET TO 1? READ THE CHANNEL STATUS BITS IN THE CHANNEL STATUS BITS PREVIOUSLY HDMI MAP 0x36 TO 0x3A READ ARE NOT VALID CS_DATA_VALID_S...
  • Page 65 Hardware User Guide UG-438 CS_DATA[1], PCM/non-PCM Audio Sample, HDMI Map, Address 0x36[1] Function CS_DATA[1] Description 0 (default) Audio sample word represents linear PCM samples Audio sample word used for other purposes CS_DATA[2], Copyright, HDMI Map, Address 0x36[2] Function CS_DATA[2] Description 0 (default) Software for which copyright is asserted Software for which no copyright is asserted...
  • Page 66 UG-438 Hardware User Guide Sampling and Frequency Accuracy The sampling frequency and clock accuracy are specified by Byte 3 of the channel status. For additional information, refer to the IEC60958 standards. CS_DATA[27:24], Sampling Frequency, HDMI Map, Address 0x39[3:0] Function CS_DATA[27:24] Description 44.1 kHz 0000 (default)

  • Page 67: Packets And Infoframes Registers

    Copyright value of channel status bit is 1. Valid only if CS_COPYRIGHT_MANUAL is set to 1. Monitoring Change of Audio Sampling Frequency ADV7610 features the NEW_SAMP_RT_RAW flag to monitor changes in the audio sampling frequency field of the channel status bits.
  • Page 68 UG-438 Hardware User Guide InfoFrame Collection Mode ADV7610 has two modes for storing the InfoFrame packet sent from the source into the internal memory. By default, the ADV7610 only stores the InfoFrame packets received if the checksum is correct for each InfoFrame.
  • Page 69 Hardware User Guide UG-438 VS_INF_CKS_ERR_RAW, IO, Address 0x8D[0] (Read Only) Status of vendor specific InfoFrame checksum error interrupt signal. When set to 1, it indicates that a checksum error has been detected for an Vendor Specific InfoFrame. Once set, this bit will remain high until it is cleared via VS_INF_CKS_ERR_CLR. Function VS_INF_CKS_ERR_RAW Description...
  • Page 70 UG-438 Hardware User Guide Audio InfoFrame Registers Table 16 provides the list of readback registers available for the Audio InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the audio InfoFrame fields. Table 16. Audio InfoFrame Registers InfoFrame Map Address Access Type Register Name Byte Name...
  • Page 71 Hardware User Guide UG-438 SPD InfoFrame Registers Table 17 provides a list of readback registers available for the SPD InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the SPD InfoFrame fields. Table 17. SPD InfoFrame Registers InfoFrame Map Address Access Type Register Name Byte Name...
  • Page 72 UG-438 Hardware User Guide MPEG Source InfoFrame Registers Table 18 provides a list of readback registers available for the MPEG InfoFrame. Refer to the EIA/CEA-861D specifications for a detailed explanation of the MPEG InfoFrame fields. Table 18. MPEG InfoFrame Registers InfoFrame Map Address Access Type Register Name...
  • Page 73 Hardware User Guide UG-438 Vendor Specific InfoFrame Registers Table 19 provides a list of readback registers available for the vendor specific InfoFrame. Table 19. VS InfoFrame Registers InfoFrame Map Address Register Name Byte Name 0xEC VS_PACKET_ID[7:0] Packet type value 0xED VS_INF_VERS InfoFrame version number 0xEE...

  • Page 74: Packet Registers

    UG-438 Hardware User Guide PACKET REGISTERS ACP Packet Registers Table 20 provides the list of readback registers available for the ACP packets. Refer to the HDMI specifications for a detailed explanation of the ACP packet fields. Table 20. ACP Packet Registers InfoFrame Map Address Register Name Packet Byte No.
  • Page 75 Hardware User Guide UG-438 ISRC Packet Registers Table 21 and Table 22 provide lists of readback registers available for the ISRC packets. Refer to the HDMI specifications for a detailed explanation of the ISRC packet fields. Table 21. ISRC1 Packet Registers InfoFrame Map Address Register Name Packet Byte No.
  • Page 76 UG-438 Hardware User Guide The ISRC1 packet registers are considered valid if ISRC1_PCKT_RAW is set to 1. ISRC1_PCKT_RAW, IO, Address 0x60[6] (Read Only) Raw status signal of International Standard Recording Code 1 (ISRC1) packet detection signal. Function ISRC1_PCKT_RAW Description 0 (default) No ISRC1 packets received since the last HDMI packet detection reset.
  • Page 77 Hardware User Guide UG-438 Gamut Metadata Packets Refer to the HDMI specifications for a detailed explanation of the gamut metadata packet fields. Table 23. Gamut Metadata Packet Registers HDMI Map Address Register Name Packet Byte No. 0xF8 GAMUT_PACKET_ID[7:0] Packet type value 0xF9 GAMUT_HEADER1 0xFA...

  • Page 78: Customizing Packet/Infoframe Storage Registers

    The packet type value of each set of packet and InfoFrame registers in the InfoFrame Map is programmable. This allows the user to configure the ADV7610 to store the payload data of any packet and InfoFrames sent by the transmitter connected on the selected HDMI port.

  • Page 79: Repeater Support

    AKSV_UPDATE_MB2 has been set to 1 This triggers the EDID/repeater controller to reset the BCAPS [5] bit back to 0. KSV List Ready KSV_LIST_READY bit is set by an external controller driving the ADV7610. This notifies the ADV7610 on-chip EDID/repeater controller that the KSV list registers have been updated with the KSV’s of the attached and active downstream HDCP devices.
  • Page 80 Repeater Bit The REPEATER bit (that is, BCAPS[7:0][6]) must be set to 1 by the external controller in the routine that initializes the ADV7610. The repeater bit must be left as such as long as the ADV7610 is configured as the front end of a repeater system.
  • Page 81 Detected a write access to the AKSV register on Port A Second and Subsequent AKSV Updates When the upstream transmitter writes its AKSV for the second time or more into the ADV7610 HDCP registers, the external controller driving the ADV7610...
  • Page 82 UG-438 Hardware User Guide BCAPS[7:0], Addr 64 (Repeater), Address 0x40[7:0] This is the BCAPS register presented to the Tx attached to the active HDMI port. Function BCAPS[7:0] Description 10000011 (default) Default BCAPS register value presented to the Tx xxxxxxxx BCAPS register value presented to the Tx BSTATUS[15:0], Addr 64 (Repeater), Address 0x42[7:0];...
  • Page 83 Hardware User Guide UG-438 KSV_MAP_SELECT[2:0], Addr 64 (Repeater), Address 0x79[6:4] Selects which 128 bytes of KSV list will be accessed when reading or writing to addresses 0x80 to 0xFF in this map. Values from 5 and upwards are not valid. Function KSV_MAP_SELECT[2:0] Description...
  • Page 84 UG-438 Hardware User Guide KSV Byte Number Register Name Register Addresses KSV_BYTE_38[7:0] 0xA6[7:0] KSV_BYTE_39[7:0] 0xA7[7:0] KSV_BYTE_40[7:0] 0xA8[7:0] KSV_BYTE_41[7:0] 0xA9[7:0] KSV_BYTE_42[7:0] 0xAA[7:0] KSV_BYTE_43[7:0] 0xAB[7:0] KSV_BYTE_44[7:0] 0xAC[7:0] KSV_BYTE_45[7:0] 0xAD[7:0] KSV_BYTE_46[7:0] 0xAE[7:0] KSV_BYTE_47[7:0] 0xAF[7:0] KSV_BYTE_48[7:0] 0xB0[7:0] KSV_BYTE_49[7:0] 0xB1[7:0] KSV_BYTE_50[7:0] 0xB2[7:0] KSV_BYTE_51[7:0] 0xB3[7:0] KSV_BYTE_52[7:0] 0xB4[7:0] KSV_BYTE_53[7:0] 0xB5[7:0]...
  • Page 85 Hardware User Guide UG-438 KSV Byte Number Register Name Register Addresses KSV_BYTE_91[7:0] 0xDB[7:0] KSV_BYTE_92[7:0] 0xDC[7:0] KSV_BYTE_93[7:0] 0xDD[7:0] KSV_BYTE_94[7:0] 0xDE[7:0] KSV_BYTE_95[7:0] 0xDF[7:0] KSV_BYTE_96[7:0] 0xE0[7:0] KSV_BYTE_97[7:0] 0xE1[7:0] KSV_BYTE_98[7:0] 0xE2[7:0] KSV_BYTE_99[7:0] 0xE3[7:0] KSV_BYTE_100[7:0] 0xE4[7:0] KSV_BYTE_101[7:0] 0xE5[7:0] KSV_BYTE_102[7:0] 0xE6[7:0] KSV_BYTE_103[7:0] 0xE7[7:0] KSV_BYTE_104[7:0] 0xE8[7:0] KSV_BYTE_105[7:0] 0xE9[7:0] KSV_BYTE_106[7:0] 0xEA[7:0]...

  • Page 86: Interface To Dpp Section

    UG-438 Hardware User Guide Register Name Address Location Function SHA_D[31:0] 0x2C[7:0]: SHA_D[7:0] H3 part of SHA-1 hash value V’ . Register also called (V’ . H3) 0x2D[7:0]: SHA_D[15:8] 0x2E[7:0]: SHA_D[23:16] 0x2F[7:0]: SHA_D[31:24] SHA_E[31:0] 0x30[7:0]: SHA_E[7:0] H4 part of SHA-1 hash value V’ . Register also called (V’ . H4) 0x31[7:0]: SHA_E[15:8] 0x32[7:0]: SHA_E[23:16] 0x33[7:0]: SHA_E[31:24]...

  • Page 87: Pass Through Mode

    This inversion ensures that for a 4:2:2 HDMI input stream no filtering will be applied if DS_WITHOUT_FILTER is left to its default value 0. When a 4:2:2 HDMI input stream is input to the ADV7610, the DPP section downsamples, without filtering, the video data from 4:4:4 to 4:2:2 format if DS_WITHOUT_FILTER is set to 0.

  • Page 88: Color Space Information Sent To The Dpp And Cp Sections

    UG-438 Hardware User Guide DPP_BYPASS_EN, Addr 44 (CP), Address 0xBD[4] Manual control to enable DPP block. Function DPP_BYPASS_EN Description 1 (default) DPP bypassed DPP enabled COLOR SPACE INFORMATION SENT TO THE DPP AND CP SECTIONS The HDMI section sends information regarding the color space of the video it outputs to the DPP and the CP sections. This color space information is derived from the DVI/HDMI status of the input stream the HDMI section processes and from the AVI InfoFrame that the HDMI section decodes from the input stream.
  • Page 89 Returns 1 if the latest general control packet received has AV_MUTE asserted. Reset to 0 following packet detection flag reset condition. INTERNAL_MUTE_RAW Returns 1 if ADV7610 has internally muted the audio data. For additional information, see the Internal Mute Status section. CS_DATA_VALID_RAW 7 (MSB) Returns 1 if channel status bit readback registers in HDMI Map, Address 0x36 to 0x3A are valid.
  • Page 90 UG-438 Hardware User Guide Table 31. HDMI Flags in IO Map Register 0x7E Bit Name Bit Position Description NEW_GAMUT_MDATA_RAW 0 (LSB) When set to 1 indicates that a gamut metadata packet with new content has been received. Once set, this bit remains high until the interrupt is cleared via NEW_GAMUT_ MDATA_PCKT_CLR.

  • Page 91: Hdmi Section Reset Strategy

    The EDID/repeater controller is reset when the DVDD supplies go low or when HDCP_REPT_EDID_RESET is set high. HDMI PACKET DETECTION FLAG RESET A packet detection flag reset is triggered when any of the following events occur: • ADV7610 is powered up. • ADV7610 is reset.

  • Page 92: Data Preprocessor And Color Space Conversion And Color Controls

    Hardware User Guide DATA PREPROCESSOR AND COLOR SPACE CONVERSION AND COLOR CONTROLS COLOR SPACE CONVERSION MATRIX ADV7610 provides any-to-any color space support. It supports formats such as RGB, YUV, YCbCr and many other color spaces. ADV7610 features a 3×3 CSC in the CP block (CP CSC), as shown in Figure 26. The CP CSC also provides color controls for brightness, contrast, saturation and hue adjustments.
  • Page 93 Reserved The selection of the CSC is automated in the ADV7610. Automatic or manual CSC mode can be selected by setting the CSC_COEFF_SEL[3:0] bits. When CSC_COEFF_SEL[3:0] is set to 0b1111, the CSC mode is automatically selected, based on the input color space and output color space required and set through the following registers: •...
  • Page 94 UG-438 Hardware User Guide RGB_OUT, IO, Address 0x02[1] A control to select output color space and the correct digital blank level and offsets on the RGB or YPrPb outputs. It is used in conjunction with the INP_COLOR_SPACE[3:0] and ALT_GAMMA bits to select the applied CSC. Function RGB_OUT Description...
  • Page 95 Hardware User Guide UG-438 HDMI Automatic CSC Operation In HDMI mode, the ADV7610 provides an automatic CSC function based on the AVI InfoFrame sent from the source. The flowchart in Figure 28 shows the mechanism of the ADV7610 auto CSC functionality in HDMI mode.
  • Page 96 YUV709 Figure 31. HDMI Auto CSC Flowchart (Case YCbCr-2) In the RGB case (refer to Figure 32), the ADV7610 has the programmability to control manually the RGB limited/full range regardless of the ITC bit. Rev. 0 | Page 96 of 184...
  • Page 97 Manual Color Space Conversion Matrix The CP CSC matrix in the ADV7610 is a 3 × 3 matrix with full programmability of all coefficients in the matrix in manual mode. Each coefficient is 12-bits wide to ensure signal integrity is maintained in the CP CSC section. The CP CSC contains three identical processing channels, one of which is shown in Figure 33.
  • Page 98 UG-438 Hardware User Guide CSC_SCALE A1[12:0] A4[12:0] ×2 OUT_A[11:0] IN_A[11:0] × A2[12:0] IN_B[11:0] × A3[12:0] IN_C[11:0] × Figure 33. Single CSC Channel The coefficients mentioned previously are detailed in Table 39 along with the default values for these coefficients. Table 39. CSC Coefficients Function Bit CP Map Address Reset Value (Hex)
  • Page 99 Hardware User Guide UG-438 CSC Manual Programming The equations performed by the CP CSC are as follows: CSC Channel A   scale × × × ×     4096 4096 4096 CSC Channel B   × ×...
  • Page 100 UG-438 Hardware User Guide The ranges of the three equations are shown in Table 40. Table 40. Equation Ranges Equation Minimum Value Maximum Value Range 0 + 0 + 0 = 0 0.59 + 0.3 + 0.11 = 1 [0 … 1] = 1 (−0.34) + (−0.17) = −0.51 0.51 [−0.51 …+ 0.51] = 1.02...

  • Page 101: Color Controls

    C4 = C2 = C1 = 0x000 (default value) A1 = B2 = C3 = 0x800 (default value) Note: The DPP CSC is always in pass-through mode unless the ADV7610 is processing an RGB input, outputting this input in the RGB color space and VID_ADJ_EN is enabled.
  • Page 102 UG-438 Hardware User Guide CP_BRIGHTNESS[7:0], Addr 44 (CP), Address 0x3C[7:0] A control to set the brightness. This field is a signed value. The effective brightness value applied to the luma is obtained by multiplying the programmed value CP_BRIGHTNESS with a gain of 4. The brightness applied to the luma has a range of [−512 to +508]. This control is functional if VID_ADJ_EN is set to 1.

  • Page 103: Component Processor

    INTRODUCTION TO THE COMPONENT PROCESSOR A simplified block diagram of the component processor (CP) on the ADV7610 is shown in Figure 34. Data is supplied to the CP from the data preprocessor (DPP). The CP circuitry is activated under the control of PRIM_MODE[3:0] and VID_STD[5:0].
  • Page 104 UG-438 Hardware User Guide CLMP_FREEZE, Addr 44 (CP), Address 0x6C[5] Stops the digital fine clamp loops for Channel A, Channel B, and Channel C from updating. Function CLMP_FREEZE Description 0 (default) Clamp value updated on every active video line Clamp loops are stopped and not updated CLMP_A_MAN, Addr 44 (CP), Address 0x6C[7] Manual clamping enable for Channel A.

  • Page 105: Cp Gain Operation

    Hardware User Guide UG-438 CLMP_C[11:0], Addr 44 (CP), Address 0x6F[3:0]; Address 0x70[7:0] Manual clamp value for Channel C. This field is an unsigned 12-bit value to be subtracted from the incoming video signal. This value programmed in this register is effective if the CLMP_BC_MAN is set to 1. To change the CLMP_C[11:0], Register Address 0x6F and Register Address 0x70 must be updated with the desired clamp value written to in this order and with no other I C access in between.
  • Page 106 UG-438 Hardware User Guide AGC_MODE_MAN GAIN_MAN HDMI_MODE SSPD DETECTED EMBEDDED SYNCS?? INPUT GAIN GAIN OP_656_RANGE OP_656_RANGE SET GAIN BASED ON RANGE A/B/C_GAIN[9:0] VALUE (255 – 0 + 1) × 0 (0 TO 255 OUTPUT) 0 (0 TO 255 OUTPUT) 16/1344 = 3.047 0 TO 255 1 (16 TO 235 Y/RGB (235 –...
  • Page 107 Hardware User Guide UG-438 A_GAIN[9:0], Addr 44 (CP), Address 0x73[5:0]; Address 0x74[7:4] A control to set the manual gain value for Channel A. This register is an unsigned value in a 2.8 binary format. To change A_GAIN[9:0], the register at Address 0x73 and Address 0x74 must be written to in this order with no I C access in between.
  • Page 108 ADV7610. The filter designed is an IIR filter with a transfer function of the form: YN = (1 −...

  • Page 109: Cp Offset Block

    The actual offset used can come from two different sources: ADV7610 includes an automatic selection of the offset value, dependent on the CSC mode that is programmed by the user. The...

  • Page 110: Av Code Block

    UG-438 Hardware User Guide A_OFFSET[9:0], Addr 44 (CP), Address 0x77[5:0]; Address 0x78[7:4] A control to set the manual offset for Channel A. This field stores an unsigned value. To change A_OFFSET[9:0], Register Address 0x77 and Register Address 0x78 must be written to in this order with no I C access in between.
  • Page 111 Hardware User Guide UG-438 AVCODE_INSERT_EN, IO, Address 0x05[2] A control to select AV code insertion into the data stream. Function AVCODE_INSERT_EN Description Does not insert AV codes into data stream 1 (default) Inserts AV codes into data stream AV_POS_SEL, Addr 44 (CP), Address 0x7B[2] A control to select AV codes position.

  • Page 112: Cp Data Path For Hdmi Modes

    Pregain Block To compensate for signal attenuation in the analog front end of the ADV7610 and input buffer gain, a pregain block is provided in the CP path. The pregain block is controlled by CP_MODE_GAIN_ADJ[7:0], which represents an unsigned value in a 1.7 binary format. The...
  • Page 113 Hardware User Guide UG-438 HDMI INPUT HDMI MEASURED VALUE CLAMP MEASUREMENT 12-BIT UNSIGNED – CLAMP CLMP_A[11:0] RGB_OUT 12-BIT CLMP_A_MAN 12'd0 HDMI_CLMP_ENABLE 12'd2056 (16 @ 8-BIT) AUTO VALUE AGC_MODE_MAN 13-BIT SIGNED GAIN_MAN PREGAIN A_GAIN[9:0] CP_OP_656_SEL* 10'd220 (×0.86) × × GAIN [0 TO 256]-IN [16 TO 235]-OUT 10-BIT 10-BIT 10'd256 (×1.00)
  • Page 114 UG-438 Hardware User Guide HDMI INPUT HDMI MEASURED VALUE CLAMP MEASUREMENT 12-BIT UNSIGNED – CLMP_B[11:0]/CLMP_C[11:0] CLAMP RGB_OUT 12-BIT CLMP_BC_MAN 12'd0 HDMI_CLMP_ENABLE 12'd2048 (128 @ 8-BIT) AUTO VALUE AGC_MODE_MAN 13-BIT SIGNED GAIN_MAN PREGAIN B_GAIN[9:0]/C_GAIN[9:0] CP_OP_656_SEL* 10'd220 (×0.86) × × GAIN [0 TO 256]-IN [16 TO 235]-OUT 10-BIT 10-BIT 10'd256 (×1.00)

  • Page 115: Sync Processed By Cp Section

    Figure 40. External/HDMI Syncs Routing to CP Section Signals Routing to Synchronization Channels ADV7610 has one synchronization channel consisting of one STDI section. When an HDMI input is applied, the HDMI core will generate HSync, VSync, and DE signals and supply them as input to the each synchronization channel shown in Figure 40. HSync from the HDMI block is denoted as HDMI_HS, and VSync from the HDMI block is denoted as HDMI_VS.
  • Page 116 UG-438 Hardware User Guide In ADV7610, there are three operational modes for the STDI block: • Continuous mode: The STDI block performs continuous measurements on lock/unlock bases and updates the corresponding I C registers based on the lock status bit (STDI_DVALID).
  • Page 117 Hardware User Guide UG-438 CH1_STDI_DVALID, Addr 44 (CP), Address 0xB1[7] (Read Only) This bit is set when the measurements performed by Sync Channel 1 STDI are completed. High level signals validity for CH1_BL, CH1_LCF, CH1_LCVS, CH1_FCL, and CH1_STDI_INTLCD parameters. To prevent false readouts, especially during signal acquisition, CH1_SDTI_DVALID only goes high after four fields with same length are recorded.
  • Page 118 UG-438 Hardware User Guide Detailed Mechanism of STDI Block Horizontal/Vertical Lock Mechanism STDI Horizontal Locking Operation For the STDI horizontal locking operation, the STDI block compares adjacent line length differences (in XTAL clock cycles) with the programmed threshold. If 128 consecutive adjacent lines lengths are within the threshold, the STDI horizontally locks to the incoming video.
  • Page 119 Hardware User Guide UG-438 FIELD2 – FIELD3 ≤ THRESHOLD? FIELD4 – FIELD5 ≤ THRESHOLD? FIELD1 – FIELD2 ≤ THRESHOLD? FIELD3 – FIELD4 ≤ THRESHOLD? FIELD 1 FIELD 2 FIELD 3 FIELD 4 FIELD 5 FIELD 6 ACTIVE VIDEO ACTIVE VIDEO ACTIVE VIDEO ACTIVE VIDEO ACTIVE VIDEO...
  • Page 120 UG-438 Hardware User Guide CH1_FCL[12:0], Addr 44 (CP), Address 0xB8[4:0]; Address 0xB9[7:0] (Read Only) A readback for the Sync Channel 1 field count length. Number of crystal clock cycles between successive VSyncs measured by Sync Channel 1 STDI or in 1/256th of a field. The readback from this field is valid if CH1_STDI_DVALID is high.
  • Page 121 Hardware User Guide UG-438 STDI Readback Values Table 46. STDI Readback Values for SD, PR, and HD Standard CHx_BL[13:0] 28.63636 MHz XTAL CHx_LCF[10:0] CHx_LCVS[4:0] FCL[12:0] 28.63636 MHz XTAL 720p SMPTE 296M 5091 4 to 5 1868 1125i SMPTE 274M 6788 562 to 563 4 to 5 1868...

  • Page 122: Cp Output Synchronization Signal Positioning

    CP OUTPUT SYNCHRONIZATION SIGNAL POSITIONING ADV7610 overall synchronization processing flow is shown in the block diagram in Figure 47. The user can reposition the synchronization signal output from the regenerated input synchronization signal within the CP block with the control bits marked in red in Figure 10.
  • Page 123 Hardware User Guide UG-438 As shown in Figure 47, the ADV7610 CP can output the following three primary and one secondary synchronization signals, which are controlled by the output control block in the CP block. Primary: • Horizontal synchronization timing reference output on the HS pin •...
  • Page 124 UG-438 Hardware User Guide CP Synchronization Signals The three primary synchronization signals have certain default positions, depending on the video standard in use. To allow for a glueless interface to downstream ICs, there is the facility to adjust the position of edges on the three primary synchronization signals.
  • Page 125 Hardware User Guide UG-438 ..... PIXEL BUS H BLANK ACTIVE VIDEO ACTIVE VIDEO HS OUTPUT START_HS[9:0] END_HS[9:0] 4 LLC1 Figure 49. HS Timing START_HS[9:0], Addr 44 (CP), Address 0x7C[3:2]; Address 0x7E[7:0] A control to shift the position of the leading edge of the HSync output by the CP core. This register stores a signed value in a twos complement format.
  • Page 126 UG-438 Hardware User Guide END_HS[9:0], Addr 44 (CP), Address 0x7C[1:0]; Address 0x7D[7:0] A control to shift the position of the trailing edge of the HSync output by the CP core. This register stores a signed value in a twos complement format. HS_END[9:0] is the number of pixel clocks by which the leading edge of the HSync is shifted (for example, 0x3FF corresponds to a shift of one pixel clock away from the active video, 0x005 corresponds to a shift of five pixel clocks toward the active video).
  • Page 127 Hardware User Guide UG-438 Function START_VS[3:0] Description 0x0 (default) Default value. 0x0 to 0x7 The leading edge of the VSync is shifted toward the active video. 0x8 to 0xF The leading edge of the VSync is shifted away from the active video. Table 56.
  • Page 128 UG-438 Hardware User Guide END_VS_EVEN[3:0], Addr 44 (CP), Address 0x89[3:0] A control to shift the position of the trailing edge of the VSync output by the CP core. This register stores a signed value in a twos complement format. SEND_VS_EVEN[3:0] is the number of lines by which the trailing edge of the VSync is shifted (for example, 0x0F corresponds to a shift of 1 line toward the active video, 0x01 corresponds to a shift of 1 line away from the active video).
  • Page 129 Hardware User Guide UG-438 DE_V_END[3:0], Addr 44 (CP), Address 0x8E[3:0] A control to vary the position of the end of the VBI region. This register stores a signed value represented in a twos complement format. The unit of DE_V_START[9:0] is one line. Function DE_V_END[3:0] Description...
  • Page 130 UG-438 Hardware User Guide Table 59. Controlling the Even Field Section of the FIELD Timing Signal START_FE[3:0] Result Note 0000(default) No move (default) Minimum → 0001 1 HS shift later than default 0011 3 HS shift later than default Maximum → 0111 7 HS shift later than default Minimum ←...
  • Page 131 Hardware User Guide UG-438 FIELD 1 15… OUTPUT VIDEO HS OUTPUT VS OUTPUT START_VS[3:0] END_VS[3:0] FIELD OUTPUT START_FO[3:0] FIELD 2 2 6 2 277… OUTPUT VIDEO HS OUTPUT VS OUTPUT END_VS[3:0] START_VS[3:0] FIELD OUTPUT START_FE[3:0] Figure 50. 525i VS Timing Rev.
  • Page 132 UG-438 Hardware User Guide FIELD 1 11… OUTPUT VIDEO HS OUTPUT VS OUTPUT START_VS[3:0] END_VS[3:0] FIELD OUTPUT START_FO[3:0] FIELD 2 323… OUTPUT VIDEO HS OUTPUT VS OUTPUT START_VS[3:0] END_VS[3:0] FIELD OUTPUT START_FE[3:0] Figure 51. 625i VS Timing OUTPUT VIDEO OUTPUT END_VS[3:0] OUTPUT START_VS[3:0]...
  • Page 133 Hardware User Guide UG-438 OUTPUT VIDEO 8… OUTPUT OUTPUT END_VS[3:0] START_VS[3:0] Figure 54. 720p VS Timing FIELD 1 OUTPUT VIDEO 1123 1124 1125 8… OUTPUT OUTPUT START_VS[3:0] END_VS[3:0] FIELD OUTPUT START_FO[3:0] FIELD 2 OUTPUT VIDEO 5 6 3 570… OUTPUT OUTPUT START_VS[3:0] END_VS[3:0]...

  • Page 134: Cp Hdmi Controls

    Free run mode provides the user with a stable clock and predictable data if the input signal cannot be decoded, for example, if input video is not present. It controls default color insertion and causes the ADV7610 to generate a default clock. The state in which this happens...
  • Page 135 Hardware User Guide UG-438 CH1_FR_LL[10:0], Addr 44 (CP), Address 0x8F[2:0]; Address 0x90[7:0] Free run line length in number of crystal clock cycles in one line of video for Sync Channel 1 STDI. This register should only be programmed video standards that are not supported by PRIM_MODE[3:0] and VID_STD[5:0]. Function CH1_FR_LL[10:0] Description...
  • Page 136 Figure 57. Free Run Field Length Selection for Channel 1 and Channel 2 Free Run Feature in HDMI Mode This section describes how to configure the free run feature when the ADV7610 is in HDMI mode. The ADV7610 HDMI mode is defined in the Primary Mode and Video Standard section.
  • Page 137 PRIM_MODE[3:0], VID_STD[5:0], and V_FREQ[2:0]. It is also possible to custom program the resolution that the ADV7610 should expect for free run Mode 1 by programming the free-run line length, line count max, and interlaced registers. Refer to the Free Run Mode section for the configuration of these registers.

  • Page 138: Cp Status

    UG-438 Hardware User Guide Table 61 shows the default colors for component and graphics based video. The values describe the color blue. Setting the CP_DEF_COL_MAN_VAL bit high enables the user to overwrite the default colors with the values given in DEF_COL_CHA[7:0], DEF_COL_CHB[7:0], and DEF_COL_CHC[7:0].

  • Page 139: Consumer Electronics Control

    CEC_SOFT_RESET Description 0 (default) No function. Reset the CEC module. Note that the CEC_POWER_UP bit can be used to set the ADV7610 to Power-Down Mode 1 (refer to the Power-Down Mode 1 section). Rev. 0 | Page 139 of 184...

  • Page 140: Cec Transmit Section

    Transmission mode disabled Transmission mode enabled and message transmission started ADV7610 features three status bits related to the transmission of CEC messages. The events that set these bits are mutually exclusive, that is, only one of the three events can occur during any given message transmission.
  • Page 141 Hardware User Guide UG-438 CEC_TX_READY_ST, IO, Address 0x93[0] (Read Only) Latched status of CEC_TX_READY_RAW signal. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. When the CEC TX successfully sends the current message this bit is set. Once set, this bit will remain high until the interrupt is cleared via CEC_TX_READY_CLR.

  • Page 142: Cec Receive Section

    UG-438 Hardware User Guide CEC RECEIVE SECTION The receive section features the hardware required for the CEC module to act as a follower. Once the CEC module is powered up via the CEC_POWER_UP bit the CEC Rx section will immediately begin monitoring the CEC bus for messages with the correct logical address(es).
  • Page 143 UG-438 Receive Buffers ADV7610 features three frame buffers that allow the receiver to receive up to three messages before the host processor needs to read a message out. When three messages have been received, no further message reception is possible until the host reads at least one message.
  • Page 144 UG-438 Hardware User Guide CEC_RX_RDY0_ST, IO, Address 0x93[3] (Read Only) Latched status of CEC_RX_RDY0_RAW signal. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. When a message has been received into Buffer 0, this bit is set. Once set, this bit will remain high until the interrupt is cleared via CEC_RX_RDY0_CLR.
  • Page 145 Hardware User Guide UG-438 CEC_BUF0_RX_FRAME_LENGTH[4:0], Addr 80 (CEC), Address 0x25[4:0] (Read Only) Function CEC_BUF0_RX_FRAME_LENGTH[4:0] Description xxxxx The total number of bytes (including header byte) that were received into Buffer 0 CEC_CLR_RX_RDY0, Addr 80 (CEC), Address 0x2C[1] (Self-Clearing) Clear control for CEC_RX_RDY0. Function CEC_CLR_RX_RDY0 Description...
  • Page 146 UG-438 Hardware User Guide Table 65. CEC Incoming Frame Buffer 2 Registers Register Name CEC Map Address Description CEC_BUF2_RX_FRAME_HEADER[7:0] 0x65 Header of message in Frame Buffer 2 CEC_BUF2_RX_FRAME_DATA0[7:0] 0x66 Byte 0 of message in Frame Buffer 2 CEC_BUF2_RX_FRAME_DATA1[7:0] 0x67 Byte 1 of message in Frame Buffer 2 CEC_BUF2_RX_FRAME_DATA2[7:0] 0x68 Byte 2 of message in Frame Buffer 2...

  • Page 147: Antiglitch Filter Module

    Hardware User Guide UG-438 Another message is received. The receiver module checks to see which of the three buffers are available, starting with Buffer 0. In this example, Buffer 0 has been read out already by the host processor and is available so the new message is stored in Receive Buffer 0. At this time the timestamp for Receive Buffer 1 is adjusted to 0b01 to show that it contains the first received message, and a timestamp of 0b10 is assigned to Receive Buffer 0 to show that it contains the second received message.

  • Page 148: Typical Operation Flow

    This section describes the algorithm that should be implemented in the host processor controlling the CEC module. Initializing CEC Module Figure 59 shows the flow that can be implemented in the host processor controlling the ADV7610 to initialize the CEC module. START...
  • Page 149 Hardware User Guide UG-438 Using CEC Module as Initiator Figure 60 shows the algorithm that can be implemented in the host processor controlling the ADV7610 to use the CEC module as an initiator. START WRITE THE OUTGOING CEC COMMAND INTO...
  • Page 150 UG-438 Hardware User Guide Using CEC Module as Follower Figure 61 shows the algorithm that can be implemented in the host processor controlling the ADV7610 to use the CEC module as a follower. START (WAIT FOR INTERRUPT) CEC_RX_RDY0_ST CEC_RX_RDY1_ST CEC_RX_RDY2_ST...

  • Page 151: Low Power Cec Message Monitoring

    UG-438 LOW POWER CEC MESSAGE MONITORING ADV7610 can be programmed to monitor the CEC line for messages that contain specific, user-programmable opcodes. These are referred to as “WAKE_OPCODEs” as they allow the system to go into a low power or sleep mode and be woken up when an opcode of interest is received, without the host processor having to check each received message.
  • Page 152 UG-438 Hardware User Guide CEC_WAKE_OPCODE4[7:0], Addr 80 (CEC), Address 0x7C[7:0] CEC_WAKE_OPCODE4 This value can be set to a CEC opcode that requires a response. On receipt of this opcode, the Rx generates an interrupt that can be used to alert the system that a CEC opcode of interest has been received and requires a response. Function CEC_WAKE_OPCODE4[7:0] Description...

  • Page 153: Interrupts

    Hardware User Guide UG-438 INTERRUPTS INTERRUPT ARCHITECTURE OVERVIEW ADV7610 interrupt architecture provides four different types of bits, namely • Raw bits • Status bits • Interrupt mask bits • Clear bits Raw bits are defined as being either edge-sensitive or level-sensitive. The following example compares AVI_INFO_RAW and NEW_AVI_INFO_RAW to demonstrate the difference.
  • Page 154 UG-438 Hardware User Guide AVI_INFO_ST, IO, Address 0x61[0] (Read Only) Latched status of AVI_INFO_RAW signal. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Once set, this bit will remain high until the interrupt is cleared via AVI_INFO_CLR. Function AVI_INFO_ST Description...
  • Page 155 Hardware User Guide UG-438 NEW_AVI_INFO_MB2, IO, Address 0x7C[0] INT2 interrupt mask for new AVI InfoFrame detection interrupt. When set a new AVI InfoFrame detection event will cause NEW_AVI_INFO_ST to be set and an interrupt will be generated on INT2. Function NEW_AVI_INFO_MB2 Description 0 (default)

  • Page 156: Interrupt Pins

    Raw bits for edge sensitive events must be cleared by the corresponding clear bit. INTERRUPT PINS ADV7610 features two dedicated interrupt pins, INT1 and INT2. INT1 is always enabled, but INT2 is disabled by default and must be enabled using the following I C control.
  • Page 157 Hardware User Guide UG-438 Interrupt Duration The interrupt duration can be programmed independently for INT1 and INT2. When an interrupt event occurs, the interrupt pin INT1 or INT2 becomes active with a programmable duration as described below. INTRQ_DUR_SEL[1:0], IO, Address 0x40[7:6] A control to select the interrupt signal duration for the interrupt signal on INT1.
  • Page 158 If an interrupt event occurs, and then a second interrupt event occurs before the system controller has cleared or masked the first interrupt event, the ADV7610 does not generate a second interrupt signal. The system controller should check all unmasked interrupt status bits as more than one may be active.

  • Page 159: Description Of Interrupt Bits

    DESCRIPTION OF INTERRUPT BITS This section lists all the raw bits in the IO map of the ADV7610 by category, and states whether the bit is an edge or level sensitive bit. A basic explanation for each bit is provided in the software manual and/or in the corresponding section of the hardware manual. For certain interrupts that require additional explanations, these are provided in the Additional Explanations section.

  • Page 160: Additional Explanations

    UG-438 Hardware User Guide • DE_REGEN_LCK_RAW • VIDEO_3D_RAW • RI_EXPIRED_A_RAW The following raw bits are all related to HDMI operation and are based on edge sensitive events; it is, therefore, necessary to clear these bits using the corresponding clear bit. •...
  • Page 161 All HDMI interrupts have a set of conditions that must be taken into account for validation in the display firmware. When the ADV7610 interrupts the display controller for an HDMI interrupt, the host must check that all validity conditions for that interrupt are met before processing that interrupt.
  • Page 162 Hardware User Guide Group 3 HDMI Interrupts The interrupts listed in Table 69 are valid under the following conditions: • ADV7610 is configured in HMDI mode • TMDS_CLK_A_RAW is set to 1 if Port A is the active HDMI port •...
  • Page 163 Hardware User Guide UG-438 Storing Masked Interrupts STORE_UNMASKED_IRQS, IO, Address 0x40[4] STORE_MASKED_IRQS allows the HDMI status flags for any HDMI interrupt to be triggered regardless of whether the mask bits are set. This bit allows a HDMI interrupt to trigger and allows this interrupt to be read back through the corresponding status bit without triggering an interrupt on the interrupt pin.
  • Page 164 UG-438 Hardware User Guide INTERRUPT_STATUS_6 register consists of fields: CP_LOCK_CH1_ST, CP_UNLOCK_CH1_ST, and STDI_DVALID_CH1_ST. CP_LOCK_CH1_ST, IO, Address 0x5C[3] (Read Only) Function CP_LOCK_CH1_ST Description 0 (default) No change. An interrupt has not been generated from this register. Channel 1 CP input has caused the decoder to go from an unlocked state to a locked state. CP_UNLOCK_CH1_ST, IO, Address 0x5C[2] (Read Only) Function CP_UNLOCK_CH1_ST...
  • Page 165 Hardware User Guide UG-438 VS_INFO_ST, IO, Address 0x61[4] (Read Only) Latched status of vendor specific InfoFrame detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via VS_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function VS_INFO_ST Description...
  • Page 166 UG-438 Hardware User Guide AV_MUTE_ST, IO, Address 0x66[5] (Read Only) Latched status of AV mute detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via AV_MUTE_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function AV_MUTE_ST Description...
  • Page 167 Hardware User Guide UG-438 Function TMDSPLL_LCK_A_ST Description 0 (default) TMDSPLL_LCK_A_RAW has not changed. An interrupt has not been generated. TMDSPLL_LCK_A_RAW has changed. An interrupt has been generated. TMDS_CLK_A_ST, IO, Address 0x6B[4] (Read Only) Latched status of Port A TMDS clock detection interrupt signal. Once set, this bit will remain high until the interrupt is cleared via TMDS_CLK_A_CLR.
  • Page 168 UG-438 Hardware User Guide HDMI Edg INT Status 1 register consists of fields: NEW_ISRC2_PCKT_ST, NEW_ISRC1_PCKT_ST, NEW_ACP_PCKT_ST, NEW_VS_INFO_ST, NEW_MS_INFO_ST, NEW_SPD_INFO_ST, and NEW_AUDIO_INFO_ST. NEW_ISRC2_PCKT_ST, IO, Address 0x7A[7] (Read Only) Latched status for the new ISRC2 packet interrupt. Once set, this bit will remain high until the interrupt is cleared via NEW_ISRC2_PCKT_CLR.
  • Page 169 Hardware User Guide UG-438 NEW_AUDIO_INFO_ST, IO, Address 0x7A[1] (Read Only) Latched status for the new audio InfoFrame interrupt. Once set, this bit will remain high until the interrupt is cleared via NEW_AUDIO_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function NEW_AUDIO_INFO_ST Description...
  • Page 170 UG-438 Hardware User Guide PACKET_ERROR_ST, IO, Address 0x7F[2] (Read Only) Latched status for the packet error interrupt. Once set, this bit will remain high until the interrupt is cleared via PACKET_ERROR_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function PACKET_ERROR_ST Description...
  • Page 171 Hardware User Guide UG-438 PARITY_ERROR_ST, IO, Address 0x84[4] (Read Only) Latched status of parity error interrupt. Once set, this bit will remain high until the interrupt is cleared via PARITY_ERROR_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function PARITY_ERROR_ST Description...
  • Page 172 UG-438 Hardware User Guide SPD_INF_CKS_ERR_ST, IO, Address 0x89[6] (Read Only) Latched status of SPD InfoFrame checksum error interrupt. Once set, this bit will remain high until the interrupt is cleared via SPD_INF_CKS_ERR_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit. Function SPD_INF_CKS_ERR_ST Description...
  • Page 173 Hardware User Guide UG-438 HDMI Edg Int Status 5 register consists of the VS_INF_CKS_ERR_ST field. VS_INF_CKS_ERR_ST, IO, Address 0x8E[0] (Read Only) Latched status of MPEG source InfoFrame checksum error interrupt. Once set, this bit will remain high until the interrupt is cleared via MS_INF_CKS_ERR_CLR.

  • Page 174: Register Access And Serial Ports Description

    UG-438 Hardware User Guide REGISTER ACCESS AND SERIAL PORTS DESCRIPTION ADV7610 has three 2-wire serial (I C compatible) ports: • One main I C port, SDA/SCL, allows a system I C master controller to control and configure the ADV7610 •...
  • Page 175 Hardware User Guide UG-438 write command to IO 0x1B, SAMPLE_ALSB, one part (with VS/FIELD/ALSB left floating) will get Address 0x98 and the second part (with VS/FIELD/ALSB pulled high) will have an address of 0x9A. SAMPLE_ALSB, IO, Address 0x1B[0] When HIGH, VS/FIELD/ALSB pin is sampled to be used as ALSB value for IO map. Function SAMPLE_ALSB Description...
  • Page 176 A Logic 1 on the LSB of the first byte means that the master will read information from the peripheral. Each of the ADV7610 maps acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit.

  • Page 177: Ddc Ports

    C port, DDC Port A, allows HDMI hosts to access the internal E-EDID and the HDCP registers. Note that the DDC ports are 5 V tolerant, which simplifies the hardware between the HDMI connector and the ADV7610. C Protocols for Access to the Internal EDID...

  • Page 178: Pcb Layout Recommendations

    In some cases, using separate ground planes is unavoidable. For those cases, it is recommended to place, at least, a single ground plane under the ADV7610. It is important to place components wisely because the current loops are much longer when using split ground planes as the current takes the path of least resistance.

  • Page 179: Digital Inputs

    28.6363MHz crystal. Figure 71 shows an example of a reference clock circuit for the ADV7610. Special care must be taken when using a crystal circuit to generate the reference clock for the ADV7610. Small variations in reference clock frequency can...

  • Page 180: Recommended Unused Pin Configurations

    UG-438 Hardware User Guide APPENDIX B RECOMMENDED UNUSED PIN CONFIGURATIONS Table 71. Recommended Configuration of Unused Pins Ball No. Mnemonic Type Description D4, D5, D6, E4, F4, G4, G5, G6 Ground Ground. HPA_A/INT2 Miscellaneous digital Float this pin. G1, G2 CVDD Power This pin is always connected to comparator supply voltage (1.8 V).
  • Page 181 Hardware User Guide UG-438 Ball No. Mnemonic Type Description INT1 Miscellaneous digital Float this pin. RESET Miscellaneous digital This level of this pin must be controlled by an external processor. XTALP Miscellaneous analog This pin is always connected to 28.63636 MHz crystal. XTALN Miscellaneous analog This pin is always connected to 28.63636 MHz crystal.

  • Page 182: Pixel Output Formats

    UG-438 Hardware User Guide APPENDIX C PIXEL OUTPUT FORMATS Table 72. SDR 4:2:2 and 4:4:4 Output Modes SDR 4:2:2 SDR 4:4:4 OP_FORMAT_SEL[7:0] 0x0A 0x80 0x8A 0x40 8-Bit SDR ITU-R 12-Bit SDR ITU-R 16-Bit SDR ITU-R 24-Bit SDR ITU-R 24-Bit SDR Pixel Output BT.656 Mode 0 BT.656 Mode 2...
  • Page 183 Hardware User Guide UG-438 Table 73. DDR 4:2:2 and 4:4:4 Output Modes DDR 4:2:2 Mode (Clock/2) DDR 4:2:2 Mode (Clock/2) DDR 4:4:4 Mode (Clock/2) 0x20 0x2A 0x60 8-Bit DDR ITU-656 12-Bit DDR ITU-656 24-Bit DDR RGB OP_FORMAT_SEL[7:0] (Clock/2 Output) 4:2:2 Mode 0 (Clock/2 Output) 4:2:2 Mode 2 (Clock/2 Output) Pixel Output...
  • Page 184 By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement.
  • Page 185 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc. EVAL-ADV7610EBZ...

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