Two muxes are used to select HSync /CSync 1 and HSync /CSync 2 from the three possible HSync signals. Similarly, two muxes are used
to select VSync 1 and VSync 2 from the three possible VS signals. These muxes are controlled by sync_ch1_hs_sel[1:0],
sync_ch1_vs_sel[1:0], sync_ch2_hs_sel[1:0], and sync_ch2_vs_sel[1:0]. The outputs of these four muxes, as well as the internal
EMB_SYNC_1 and EMB_SYNC_2 signals from the sync slicers (as described in Section 9.6.1) are passed to a clock registering and
deglitch block.
sync_ch1_hs_sel[1:0], IO, Address 0x07[5:4]
This control is used to select the HSync input to sync channel 1.
Function
sync_ch1_hs_sel[1:0]
00
01
10
11
sync_ch1_vs_sel[1:0], IO, Address 0x07[3:2]
This control is used to select the VSync input to sync channel 1.
Function
sync_ch1_vs_sel[1:0]
00
01
10
11
sync_ch2_hs_sel[1:0], IO, Address 0x08[5:4]
This control is used to select the HSync input to sync channel 2.
Function
sync_ch2_hs_sel[1:0]
00
01
10
11
sync_ch2_vs_sel[1:0], IO, Address 0x08[3:2]
This control is used to select the VSync input to sync channel 2.
Function
sync_ch2_vs_sel[1:0]
00
01
10
11
9.6.2.2 XTAL Clock Registering and Glitch Rejection Filter
As shown in
Figure
86, the XTAL CLOCK REGISTERING BLOCK and DIGITAL GLITCH REJECTION FILTER have two outputs for
Rev. A May 2012
Description
Auto-select mode; hs_in1 or HSync from HDMI (HDMI-HS) set to channel 1 based on primary
mode set in prim_mode[3:0]. HDMI-HS selected in HDMI mode. HS1 input selected in
component or graphics mode.
Select hs_in1
Select hs_in2
HDMI-HS
Description
Auto-select mode; vs_in1 or VSync from HDMI (HDMI-VS) set to channel 1 based on primary
mode set in prim_mode[3:0]. HDMI-VS selected in HDMI mode. VS1 input selected in
component or graphics mode.
Select vs_in1 input
Select vs_in2 input
Reserved
Description
Select HS2 input
Select HS1 input
Select HS2 input
Select HDMI HS
Description
Select VS2 input
Select VS1 input
Select VS2 input
Select HDMI VS
260
ADV7850
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