Scart Source Selection Control; Scart Fast Blank Timing - Analog Devices ADV7850 Hardware Manual

The fast blank position resolver determines the time position of the fast blank to a very high accuracy and this position information is
then used by the subpixel blender in dynamic switching modes. This enables the ADV7850 to implement high performance multiplexing
between the CVBS and RGB sources, even when the RGB data source is completely asynchronous to the sampling crystal reference.
The switched or blended data is output from the ADV7850 in the standard formats that exist for the SDP.

SCART Source Selection Control

5.8.11
sdp_man_fb_en, Addr 90 (SDP), Address 0x2A[3]
This control is used to select between manual fast blank control via sdp_man_fb and automatic fast blank control via the FB signal
(refer to fb_select in the AFE Map).
Function
sdp_man_fb_en
1
0 
sdp_man_fb, Addr 90 (SDP), Address 0x2A[7]
This control is used to select a video source for fast blank operation. This control is only valid sdp_man_fb_en is set to 1.
Function
sdp_man_fb
1
0 

SCART Fast Blank Timing

5.8.12
The critical information extracted from the SCART fast blank signal is the time at which it switches relative to the input video. Due to
small timing inequalities, either on the IC or on the PCB, it may be necessary to adjust the result by fractions of one clock cycle. This is
controlled by fb_phase_adjust[3:0].
Each LSB of fb_phase_adjust[3:0]
SCART fast blank signal. The reset value is chosen to give equalized channels when the ADV7850 internal anti aliasing filters are enabled
and there is no unintentional delay on the PCB.
fb_phase_adjust[3:0], Addr 4C (DPLL), Address 0xC9[3:0]
This control is used to adjust the phase of the fast blank signals in order to correct the delay the signal endures.
Function
fb_phase_adjust[3:0]
0000 <<
sdp_fb_delay_adj[2:0], Addr 90 (SDP), Address 0x2A[2:0]
This signed control is used to advance or delay for FB signal in increments of one burst-locked pixel.
Rev. A May 2012
Description
Allow manual control of FB signal
Auto fast blank controlled by FB signal
Description
Select RGB
Select CVBS
corresponds to 1/8 of an ADC clock cycle. Increasing the value is equivalent to adding delay to the
Description
Default
65
ADV7850