Memory Controller; Memory Requirements; General Controls; Reset - Analog Devices ADV7850 Hardware Manual

12 MEMORY CONTROLLER

12.1

MEMORY REQUIREMENTS

The ADV7850 supports a DDR2 memory interface. Depending on the feature required, the appropriate memory device can be selected.
The external memory is required for 3D comb and Frame TBC operation only.
The ADV7850 requires the following memory specifications:
• 128 Mb, 256 Mb, 512 Mb and 1Gb DDR2 SDRAM memory are supported
• Memory architecture supports bus width of 16 bits
• Minimum speed grade of 108 MHz and an integer CAS latency is required
• Example of 512 Mb compatible memory includes Micron MT47H32M16HR-25EG
• 47 Ω series termination resistors are recommended for this configuration

GENERAL CONTROLS

12.2

Reset

12.2.1
A reset should be carried out after changes to the memory configuration. The reset is required before the configuration settings are
implemented in the ADV7850.
sdp_mem_reset, IO, Address 0xFF[2] (Self-Clearing)
Memory interface reset.
Function
sdp_mem_reset
0 <<
1

Output Enables

12.2.2
ddr2_ck_oe, XMEM_GAMMA, Address 0x28[6]
This control is used to enable the external memory clock signal.
Function
ddr2_ck_oe
0 
1
rw_ctrl_oe, XMEM_GAMMA, Address 0x28[7]
This control is used to enable the external memory read/write signals, e.g. ras, cas, clock, and address.
Rev. A May 2012
Description
Not reset
Apply SDP Memory reset
Description
Input
Output
344
ADV7850