Table 32: Isrc2 Packet Registers - Analog Devices ADV7850 Hardware Manual

InfoFrame
Map Address
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
As defined by the HDMI 1.4 specifications
1
The ISRC1 packet registers are considered valid if
isrc1_pckt_raw, IO, Address 0x60[6] (Read Only)
This readback indicates the raw status signal of the International Standard Recording Code 1 (ISRC1) packet detection signal. This bit
resets to 0 after an HDMI packet detection reset or upon writing to isrc1_packet_id.
Function
isrc1_pckt_raw
0 
1
InfoFrame
Map Address
0xF5
0xF6
0xF7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
0xC0
0xC1
0xC2
0xC3
As defined by the HDMI 1.4 specifications
1
Rev. A May 2012
R/W Register Name
R isrc1_pb_0_20
R isrc1_pb_0_21
R isrc1_pb_0_22
R isrc1_pb_0_23
R isrc1_pb_0_24
R isrc1_pb_0_25
R isrc1_pb_0_26
R isrc1_pb_0_27
R isrc1_pb_0_28
isrc1_pckt_raw
Description
No ISRC1 packets received since last HDMI packet detection reset.
ISRC1 packets received.

Table 32: ISRC2 Packet Registers

R/W Register Name
R/W isrc2_packet_id[7:0]
R isrc2_header1
R isrc2_header2
R isrc2_pb_0_1
R isrc2_pb_0_2
R isrc2_pb_0_3
R isrc2_pb_0_4
R isrc2_pb_0_5
R isrc2_pb_0_6
R isrc2_pb_0_7
R isrc2_pb_0_8
R isrc2_pb_0_9
R isrc2_pb_0_10
R isrc2_pb_0_11
R isrc2_pb_0_12
R isrc2_pb_0_13
R isrc2_pb_0_14
R isrc2_pb_0_15
R isrc2_pb_0_16
R isrc2_pb_0_17
R isrc2_pb_0_18
R isrc2_pb_0_19
R isrc2_pb_0_20
R isrc2_pb_0_21
R isrc2_pb_0_22
R isrc2_pb_0_23
R isrc2_pb_0_24
R isrc2_pb_0_25
R isrc2_pb_0_26
R isrc2_pb_0_27
R isrc2_pb_0_28
Packet Byte No.
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
is set to 1.
Packet Byte No.
Packet Type Value
HB1
HB2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
209
ADV7850
1
1