Hdmi Receiver Section Reset Strategy; Hdmi Packet Detection Flag Reset; Table 44: Hdmi Infoframe Checksum Error Flags In Io Map; Table 45: Aksv Update Flags In Io Map Register 0X88 - Analog Devices ADV7850 Hardware Manual

Bit Name Bit
Position
aksv_update_d_raw 0 (LSB)
aksv_update_c_raw 1
aksv_update_b_raw 2
aksv_update_a_raw 3

7.42 HDMI RECEIVER SECTION RESET STRATEGY

The reset strategy implemented for the HDMI receiver section is described here.
Global Chip Reset
A global chip reset is triggered by asserting the RESET pin to a low level. The HDMI section, excluding the E-EDID/Repeater controller, is
reset when a global reset is triggered.
Loss of TMDS Clock or 5 V Signal Reset
A loss of TMDS clock or 5 V signal on the HDMI port selected via
E-EDID/Repeater controller and the audio section. The loss of a 5 V signal condition is discarded if
DVI Mode Reset
The packet processing block, including InfoFrame memory, is held in reset when the HDMI section processes a DVI stream.
E-EDID/Repeater Controller Reset
The E-EDID/Repeater controller is reset when the DVDD supplies go low or when

7.43 HDMI PACKET DETECTION FLAG RESET

A packet detection flag reset is triggered when any of the following events occur:
• The ADV7850 is powered up.
• The ADV7850 is reset.
• A TMDS clock is detected after a period of no clock activity on the selected HDMI port.
• The selected HDMI port is changed.
• The signal from the 5 V input pin of the HDMI port selected through HDMI_PORT_SELECT transitions to a high. This
condition is discarded if
Rev. A May 2012

Table 44: HDMI InfoFrame Checksum Error Flags in IO Map

Bit Name
avi_inf_cks_err_raw
aud_inf_cks_err_raw
spd_inf_cks_err_raw
ms_inf_cks_err_raw
vs_inf_cks_err_raw

Table 45: AKSV Update Flags in IO Map Register 0x88

Description
When set to 1, indicates that transmitter has written its AKSV into HDCP registers for Port D. Once set,
remains high until interrupt cleared via aksv_update_d_clr (IO Map 0x8A [0]).
When set to 1, indicates that transmitter has written its AKSV into HDCP registers for Port C. Once set,
remains high until interrupt cleared via aksv_update_c_clr (IO Map 0x8A [1]).
When set to 1, indicates that transmitter has written its AKSV into HDCP registers for Port B. Once set,
remains high until interrupt cleared via aksv_update_b_clr (IO Map 0x8A [2]).
When set to 1, indicates that transmitter has written its AKSV into HDCP registers for Port A. Once set,
remains high until interrupt cleared via aksv_update_a_clr (IO Map 0x8A [3]).
Bit Name
audio_pll_locked
audio_sample_pckt_det
dsd_packet_det
hbr_audio_packet_det
dcfifo_locked
dis_cable_det_rst is set to 1.
IO Map Location Description
0x88[4] Description available on page
0x88[5] Description available on page
0x88[6] Description available on page
0x88[7] Description available on page
0x8D[0] Description available on page

Table 46: HDMI Flags in HDMI Map

HDMI Map Location Description
0x04[0] Description available on page
0x18[0] Description available on page
0x18[1] Description available on page
0x18[3] Description available on page
0x1C[3] Description available on page
hdmi_port_select[2:0]
225
201
201
201
202
202
178
181
181
181
161
resets the entire HDMI section except for the
dis_cable_det_rst
hdcp_rept_edid_reset is set to 1.
ADV7850
is set to 1.