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Operation
4 Operation
A functional block diagram of the Apps FPGA is shown in
modules that perform each set of functions, with VHDL module names in italics.
The Apps FPGA has three operating states:
1. Initializing
2. Initialization error
3. Run
a. Test pattern / Apps DLP load control
b. User DLP load control
The Apps FPGA performs initialization and responds to initialization errors, as described in the
(0x0040)
section. Once initialization is complete, the run state begins. In the run state, there are two independent
DLP control methods selected by bit zero of the loader control register
test pattern Apps FPGA loader control of the DLP component set. The second is when the Apps FPGA loader is
not in control, the DLP component set can be controlled through the USB GPIF interface (user control mode).
4.1 Initialization
The Apps FPGA provides the DLPC910 and attached DMD chip set initialization per the DLPC910 data sheet
requirements. VHDL module irp.vhd (init-run-park control) and the sub-module irp_fsm.vhd (init-run-park state
machine) provide this startup logic.
4.1.1 Initialization Prompts
Any of the following events cause the init-run-park state machine to execute the initialization routine:
1. Completion of the Apps FPGA configuration.
2. Pressing SW1 APP RST switch on DLPLCRC910EVM (apps_resetz to the Apps FPGA).
3. ON to OFF transition by position 1 of dip switch SW2 on DLPLCRC910EVM (un-parking the system using
dip switch).
4. '1' to '0' transition of park bit in USB GPIF register 0x0044 (for example, un-parking the system using register
command bit).
®
14
DLP
DLPC910 Apps FPGA Guide
Figure 4-1. Apps FPGA Functional Block Diagram
Copyright © 2023 Texas Instruments Incorporated
Figure
4-1. The overlay colors highlight the VHDL
(Loader Control
www.ti.com
Loader Control
(0x0040)). The first is the
DLPU125 – JUNE 2023
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