Table of Contents
Advertisement
363-206-285
Issue 2, February 2000
Table B – BBF2B/BBF2C TGS/BBF4 TG3 Synchronization Provisioning Topologies
NE 1
External - Sync Out
External - Sync Out
External - Mult
NE 2
Line Timing
Line Timing - Sync Out
External - Mult
DDM-2000 OC-3 M
Detailed Level Procedure:
Application Comments
Caution! This topology might create a timing loop. In this
topology the NE provisioned for Line Timing will derive its
timing from the NE provisioned for External - Sync Out
timing thus operating synchronously with that respective
NE. The NE provisioned for External - Sync Out should
be reprovisioned for External - Mult to prevent the
potential timing loop existing in the actual provisioning. If
Synchronization Messaging is enabled on both NE's, the
DS1 output reference of the NE provisioned for External -
Sync out will carry an unframed all ones DS1 signal (DS1
AIS) in the present topology. If automatic synchronization
reconfiguration is supported and enabled in a system,
both NEs will attempt to break the potential timing loop.
NE 1 will attempt to break the timing loop by inserting
DS1 AIS on its DS1 output port. NE 2 will attempt to
switch to another line timing source, if available, to
prevent the timing loop.
Caution! This topology might create a timing loop. In this
topology the NE provisioned for Line Timing will derive its
timing and that of the DS1 output reference from the NE
provisioned for External - Sync Out timing thus operating
synchronously with that respective NE. The NE
provisioned for External - Sync Out should be
reprovisioned for External - Mult to prevent the timing
loop existing in the actual provisioning. If Synchronization
Messaging is enabled on both NE's, the DS1 output
reference on NE 1 will carry DS1 AIS and NE 2 will derive
its timing and that of the DS1 output port from NE 1. If
automatic synchronization reconfiguration is supported
and enabled in a system, both NEs will attempt to break
the potential timing loop. NE 1 will attempt to break the
timing loop by inserting DS1 AIS on its DS1 output port.
NE 2 will attempt to switch to another line timing source, if
available, to prevent the timing loop.
This topology is used when both NE's have access to and
are receiving its timing from BITS clocks. The
recommendation is to have these BITS synchronized to
references which are traceable to the same PRS. If these
guidelines are followed the subnetwork created by these
two NE's would be operating synchronously. Note
DDM-2000 systems are designed to operate in
pleisiochronous timing topologies. The DS1 output
generated by each NE is regenerated from the input DS1
timing reference and could be used to distribute this
reference to other shelves colocated in the same bay to
conserve ports on the BITS.
ULTIPLEXER
DLP-503
Page 4 of 10
Hide quick links:
Advertisement
Table of Contents
