Data Byte Ordering - IBM PPC440X5 CPU Core User Manual

Preliminary
On the other hand, in a little endian mapping the same instruction is arranged with the least-significant byte
(LSB) of the instruction word at the lowest-numbered address:
By the definition of PowerPC Book-E bit numbering, the most-significant byte of an instruction is the byte
containing bits 0:7 of the instruction. As depicted in the instruction format diagrams (see Instruction Formats
on page 250), this most-significant byte is the one which contains the primary opcode field (bits 0:5). Due to
this difference in byte orderings, the processor must perform whatever byte reversal is required (depending
on the particular byte ordering in use) in order to correctly deliver the opcode field to the instruction decoder.
In the PPC440x5, this reversal is performed between the memory interface and the instruction cache,
according to the value of the endian storage attribute for each memory page, such that the bytes in the
instruction cache are always correctly arranged for delivery directly to the instruction decoder.
If the endian storage attribute for a memory page is reprogrammed from one byte ordering to the other, the
contents of the memory page must be reloaded with program and data structures that are in the appropriate
byte ordering. Furthermore, anytime the contents of instruction memory change, the instruction cache must
be made coherent with the updates by invalidating the instruction cache and refetching the updated memory
contents with the new byte ordering.

2.1.3.3 Data Byte Ordering

Unlike instruction fetches, data accesses cannot be byte-reversed between memory and the data cache.
Data byte ordering in memory depends upon the data type (byte, halfword, word, and so on) of a specific data
item. It is only when moving a data item of a specific type from or to an architected register (as directed by the
execution of a particular storage access instruction) that it becomes known what kind of byte reversal may be
required due to the byte ordering of the memory page containing the data item. Therefore, byte reversal
during load or store accesses is performed between data cache (or memory, on a data cache miss, for
example) and the load register target or store register source, depending on the specific type of load or store
instruction (that is, byte, halfword, word, and so on).
Comparing the big endian and little endian mappings of structure
on page 43, the differences between the byte locations of any data item in the structure depends upon the
size of the particular data item. For example (again referring to the big endian and little endian mappings of
s ):
structure
• The word a has its four bytes reversed within the word spanning addresses 0x00 – 0x03.
• The halfword e has its two bytes reversed within the halfword spanning addresses 0x1C – 0x1D.
Note that the array of bytes d, where each data item is a byte, is not reversed when the big endian and little
endian mappings are compared. For example, the character 'A' is located at address 0x14 in both the big
endian and little endian mappings.
The size of the data item being loaded or stored must be known before the processor can decide whether,
and if so, how to reorder the bytes when moving them between a register and the data cache (or memory).
• For byte loads and stores, including strings, no reordering of bytes occurs, regardless of byte ordering.
• For halfword loads and stores, bytes are reversed within the halfword, for one byte order with respect to
the other.
prgmodel.fm.
September 12, 2002
LSB
0x00 0x01 0x02
MSB
0x03
s , as shown in Structure Mapping Examples
User's Manual
PPC440x5 CPU Core
Page 45 of 589