Figure 4-7. Instruction Cache Debug Data Register (Icdbdr); Figure 4-8. Instruction Cache Debug Tag Register High (Icdbtrh); Figure 4-9. Instruction Cache Debug Tag Register Low (Icdbtrl) - IBM PPC440X5 CPU Core User Manual

Preliminary
mficdbdr regC
mficdbtrh regD
mficdbtrl regE
The following figures illustrate the ICDBDR, ICDBTRH, and ICDBTRL.
0

Figure 4-7. Instruction Cache Debug Data Register (ICDBDR)

0:31 Instruction machine code from instruction cache
0

Figure 4-8. Instruction Cache Debug Tag Register High (ICDBTRH)

0:23 Tag Effective Address
Cache Line Valid
0 Cache line is not valid.
24 V
1 Cache line is valid.
25:26 TPAR Tag Parity
27 DAPAR Instruction Data parity
28:31 Reserved
0

Figure 4-9. Instruction Cache Debug Tag Register Low (ICDBTRL)

0:21 Reserved
22 TS Translation Space
cache.fm.
September 12, 2002
# move instruction information into GPR C
# move high portion of tag into GPR D
# move low portion of tag into GPR E
TEA
TPAR
23 24 25 26 27 28
DAPAR
V
Bits 0:23 of the 32-bit effective address associated
with the cache line read by icread.
The valid indicator for the cache line read by
icread.
The parity bits for the address tag for the cache
line read by icread, if CCR0[CRPE] is set.
The parity bit for the instruction word at the 32-bit
effective address specified in the icread instruc-
tion, if CCR0[CRPE] is set.
TS
21 22 23 24
TD
The address space portion of the virtual address
associated with the cache line read by icread.
User's Manual
PPC440x5 CPU Core
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