Operand Conventions; Data Organization In Memory And Data Transfers; Alignment And Misaligned Accesses; Table 2-4. Memory Operands - IBM PowerPC 750GX User Manual

User's Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor

2.2 Operand Conventions

This section describes the operand conventions as they are represented in two levels of the PowerPC Archi-
tecture—UISA and VEA. Detailed descriptions of conventions used for storing values in registers and
memory, accessing PowerPC registers, and representing data in these registers can be found in Chapter 3,
"Operand Conventions" in the PowerPC Microprocessor Family: The Programming Environments Manual.

2.2.1 Data Organization in Memory and Data Transfers

Bytes in memory are numbered consecutively starting with 0. Each number is the address of the corre-
sponding byte.
Memory operands can be bytes, half words, words, or double words, or, for the load/store multiple and
load/store string instructions, a sequence of bytes or words. The address of a memory operand is the address
of its first byte (the lowest-numbered byte). Operand length is implicit for each instruction.

2.2.2 Alignment and Misaligned Accesses

The operand of a single-register memory-access instruction has an alignment boundary equal to its length.
An operand's address is misaligned if it is not a multiple of its width. Operands for single-register memory-
access instructions have the characteristics shown in Table 2-4. Although not permitted as memory oper-
ands, quadwords are shown because quadword alignment is desirable for certain memory operands.

Table 2-4. Memory Operands

Operand
Byte
Half word
Word
Double word
Quadword
Note: An "x" in an address bit position indicates that the bit can be 0 or 1 independent of the state of other bits in the address.
The concept of alignment is also applied more generally to data in memory. For example, a 12-byte data item
is said to be word-aligned if its address is a multiple of four.
Some instructions require their memory operands to have a certain alignment. In addition, alignment can
affect performance. For single-register memory-access instructions, the best performance is obtained when
memory operands are aligned. Instructions are 32 bits (one word) long and must be word-aligned.
The 750GX does not provide hardware support for floating-point memory that is not word-aligned. If a
floating-point operand is not aligned, the 750GX invokes an alignment exception, and it is left up to software
to break up the offending storage access operation appropriately. In addition, some non-double-word–aligned
memory accesses suffer performance degradation as compared to an aligned access of the same type.
In general, floating-point word accesses should always be word-aligned, and floating-point double-word
accesses should always be double-word–aligned. Frequent use of misaligned accesses is discouraged since
they can degrade overall performance.
Programming Model
Page 82 of 377
Length
8 bits
2 bytes
4 bytes
8 bytes
16 bytes
Addr[28-31] If Aligned
xxxx
xxx0
xx00
x000
0000
gx_02.fm.(1.2)
March 27, 2006