Instruction Storage Interrupt - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core
AP Set to 1 if the instruction causing the interrupt is an auxiliary processor load or store;
otherwise set to 0.
BO Set to 1 if the instruction caused a Byte Ordering exception; otherwise set to 0. Note
that a Read or Write Access Control exception may occur in combination with a Byte
Ordering exception, in which case software would need to examine the TLB entry
associated with the address reported in the DEAR to determine whether both
exceptions had occurred, or just a Byte Ordering exception.
MCI Unchanged.
All other defined ESR bits are set to 0.

6.5.4 Instruction Storage Interrupt

An Instruction Storage interrupt occurs when no higher priority exception exists and an Instruction Storage
exception is presented to the interrupt mechanism. Note that although an Instruction Storage exception may
occur during an attempt to fetch an instruction, such an exception is not actually presented to the interrupt
mechanism until an attempt is made to execute that instruction. The PPC440x5 core includes one type of
Instruction Storage exception. That is:
Execute Access Control exception
An Execute Access Control exception is caused by one of the following:
• While in user mode (MSR[PR] = 1), an instruction fetch attempts to access a location in storage that
is not enabled for execute access in user mode (that is, the TLB entry associated with the memory
page being accessed has UX = 0).
• While in supervisor mode (MSR[PR] = 0), an instruction fetch attempts to access a location in storage
that is not enabled for execute access in supervisor mode (that is, the TLB entry associated with the
memory page being accessed has SX = 0).
Architecture Note: The PowerPC Book-E architecture defines an additional Instruction
When an Instruction Storage interrupt occurs, the processor suppresses the execution of the instruction
causing the Instruction Storage exception, the interrupt processing registers are updated as indicated below
(all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] ||
IVOR3[IVO] || 0b0000.
Save/Restore Register 0 (SRR0)
Set to the effective address of the instruction causing the Instruction Storage interrupt.
Save/Restore Register 1 (SRR1)
Set to the contents of the MSR at the time of the interrupt.
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Storage exception -- the Byte Ordering exception. This exception is
defined to assist implementations that cannot support dynamically
switching byte ordering between consecutive instruction fetches
and/or cannot support a given byte order at all. The PPC440x5 core
however supports instruction fetching from both big endian and little
endian memory pages, so this exception cannot occur.
Preliminary
intrupts.fm.
September 12, 2002