User And Supervisor Modes; Privileged Instructions; Table 2-27. Privileged Instructions - IBM PPC440X5 CPU Core User Manual

User's Manual
PPC440x5 CPU Core
U1 Storage Attribute
0 U1 storage attribute is disabled
17 U1
1 U1 storage attribute is enabled
U2 Storage Attribute
0 U2 storage attribute is disabled
18 U2
1 U2 storage attribute is enabled
U3 Storage Attribute
0 U3 storage attribute is disabled
19 U3
1 U3 storage attribute is enabled
20:23 Reserved
E Storage Attribute
0 Accesses to the page are big endian.
24 E
1 Accesses to the page are little endian.
25:27 Reserved
28:31 ERPN Extended Real Page Number

2.8 User and Supervisor Modes

PowerPC Book-E architecture defines two operating "states" or "modes," supervisor (privileged), and user
(non-privileged). Which mode the processor is operating in is controlled by MSR[PR]. When MSR[PR] is 0,
the processor is in supervisor mode, and can execute all instructions and access all registers, including privi-
leged ones. When MSR[PR] is 1, the processor is in user mode, and can only execute non-privileged instruc-
tions and access non-privileged registers. An attempt to execute a privileged instruction or to access a
privileged register while in user mode causes a Privileged Instruction exception type Program interrupt to
occur.
Note that the name "PR" for the MSR field refers to an historical alternative name for user mode, which is
"problem state." Hence the value 1 in the field indicates "problem state," and not "privileged" as one might
expect.

2.8.1 Privileged Instructions

The following instructions are privileged and cannot be executed in user mode:

Table 2-27. Privileged Instructions

dcbi
dccci
dcread
iccci
icread
mfdcr
Page 80 of 589
See Table 5-1 on page 135.
See Table 5-1 on page 135.
See Table 5-1 on page 135.
This TLB field is prepended to the translated
address to form a 36-bit real address. See Table
5.4 Address Translation on page 140 and Table
5-3 Page Size and Real Address Formation on
page 142.
Preliminary
prgmodel.fm.
September 12, 2002