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Preliminary
Table 2-25. XER[SO,OV] Updating Instructions
Integer Arithmetic
Add
Subtract
addo
.
subfo
.
[
]
[
]
addco
.
subfco
.
[
]
[
]
addeo
.
subfeo
.
[
]
[
]
addmeo
.
subfmeo
[
]
[
addzeo
.
subfzeo
.
[
]
[
2.6.2.1 Summary Overflow (SO) Field
This field is set to 1 when an instruction is executed that causes XER[OV] to be set to 1, except for the case
of
mtspr (XER), which writes XER[SO,OV] with the values in (RS)
reset until either an
mtspr (XER) is executed with data that explicitly writes 0 to XER[SO], or until an mcrxr
instruction is executed. The mcrxr instruction sets XER[SO] (as well as XER[OV,CA]) to 0 after copying all
three fields into CR[CR0]
Given this behavior, XER[SO] does not necessarily indicate that an overflow occurred on the most recent
integer arithmetic operation, but rather that one occurred at some time subsequent to the last clearing of
XER[SO] by mtspr(XER) or mcrxr.
XER[SO] is read (along with the rest of the XER) into a GPR by mfspr(XER). In addition, various integer
instructions copy XER[SO] into CR[CR0]
prgmodel.fm.
September 12, 2002
Multiply
Divide
divwo
.
[
]
mullwo
.
[
]
divwuo
.
[
]
.
]
]
Table 2-26. XER[CA] Updating Instructions
Integer Arithmetic
Add
Subtract
subfc
addc
o
.
[
[
][
]
subfe
adde
o
.
[
[
][
]
addic
.
subfic
[
]
addme
o
.
[
][
]
subfme
addze
o
.
[
][
]
subfze
(and setting CR[CR0]
0:2
(see Condition Register (CR) on page 67).
3
Auxiliary Processor
Multiply-Accumu-
Negate
late
macchwo
.
[
macchws
o[
macchwsu
macchwu
o[
machhw
.
o[
machhws
o[
nego
.
[
]
machhwsu
machhwu
o[
maclhw
.
o[
]
maclhws
.
o[
maclhwsu
o[
maclhwu
o[
Integer
Processor
Shift
Control
Shift
Register
Right
Management
Algebraic
o
.
][
]
o
.
][
]
mtspr
sraw
.
[
]
srawi
.
[
]
mcrxr
o
.
[
][
]
o
.
[
][
]
, respectively. Once set, XER[SO] is not
0:1
to 0).
3
PPC440x5 CPU Core
Processor Con-
Negative Multi-
Register Man-
ply- Accumulate
]
.
]
.
o[
]
.
nmacchw
.
]
o[
]
nmacchws
.
]
o[
]
mtspr
.
nmachhw
.
]
o[
]
.
nmachhws
.
o[
]
o[
]
mcrxr
.
nmaclhw
.
]
o[
]
nmaclhws
.
o[
]
]
.
]
.
]
Page 73 of 589
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