Register 1: Status Register Bit Definitions - Intel GD82559ER Datasheet

Fast ethernet** pci controller
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GD82559ER — Networking Silicon
Bit(s)
9
8
7
6:0
9.1.2

Register 1: Status Register Bit Definitions

Bit(s)
15
14
13
12
11
10:7
6
5
4
3
2
1
0
66
Name
Restart Auto-
This bit restarts the Auto-Negotiation process and is self-
Negotiation
clearing.
1 = Restart Auto-Negotiation process
Duplex Mode
This bit controls the duplex mode when Auto-Negotiation
is disabled. If the PHY reports that it is only able to
operate in one duplex mode, the value of this bit shall
correspond to the mode which the PHY can operate.
When the PHY is placed in Loopback mode, the behavior
of the PHY shall not be affected by the status of this bit,
bit 8.
1 = Full Duplex
0 = Half Duplex
Collision Test
This bit will force a collision in response to the assertion
of the transmit enable signal.
1 = Force COL
0 = Do not force COL
Reserved
These bits are reserved and should be set to 0000000b.
Name
Reserved
This bit is reserved and should be set to 0b.
100BASE-TX Full
1 = PHY able to perform full duplex 100BASE-TX
Duplex
100 Mbps Half
1 = PHY able to perform half duplex 100BASE-TX
Duplex
10 Mbps Full
1 = PHY able to operate at 10Mbps in full duplex
Duplex
mode
10 Mbps Half
1 = PHY able to operate at 10 Mbps in half duplex
Duplex
mode
Reserved
These bits are reserved and should be set to 0000b.
Management
0 = PHY will not accept management frames with
Frames Preamble
preamble suppressed
Suppression
Auto-Negotiation
1 = Auto-Negotiation process completed
Complete
0 = Auto-Negotiation process has not completed
Remote Fault
0 = No remote fault condition detected
Auto-Negotiation
1 = PHY is able to perform Auto-Negotiation
Ability
Link Status
1 = Valid link has been established
0 = Invalid link detected
Jabber Detect
1 = Jabber condition detected
0 = No jabber condition detected
Extended
1 = Extended register capabilities enabled
Capability
Description
Description
Default
R/W
0
RW
SC
0
RW
0
RW
0
RW
Default
R/W
0
RO
E
1
RO
1
RO
1
RO
1
RO
0
RO
0
RO
0
RO
0
RO
1
RO
0
RO
LL
0
RO
LH
1
RO
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