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5.4.
INITIALIZATION PROCESS
After establishing configuration options, a processor executes the following initialization
actions:
•
Synchronize the internal phase-locked loop (PLL) used to derive the processor clock
from the bus clock.
•
Configure the parallel bus arbiter based on the processor's agent ID and FRC enable pin.
Configure the APIC bus arbiter ID with additional information available via APIC
cluster ID.
•
If enabled by the configuration options, begin execution of the built-in self test (BIST).
•
Begin fetching and executing code from the reset address, 00_FFFF_FFF0H or
00_000F_FFF0.
During initialization, each processor begins active BNR# sequencing from the RESET#
signal's active-to-inactive transition until it is able to accept (though not necessarily issue)
bus transactions.
Signals that have special meanings during initialization assume their normal roles for a
particular processor when the processor first asserts ADS# after a reset.
Each processor can obtain its power-on-configuration information from a 32-bit register in
the MSR space. This register can be read by the initialization software and different
processors can then be initialized differently based on their agent ID.
When the reset condition is generated by the activation of RESET#, BPRI# and BNR# must
be sampled inactive together on a valid BNR# sampling point, to allow new request
generation by a symmetric agent.
CONFIGURATION
5-9
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