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3. Programming Model
NII-PRG | 2018.04.18
flushing the pipeline as needed (either by using a
instruction to a register that does flush the pipeline). Because a context switch
typically requires reprogramming the MPU regions for the new thread, flushing the
pipeline on each
3.5.2. MPU Initialization
Your system software must provide a data structure that contains the region
information described in the "Memory Regions" section of this chapter for each active
thread. The data structure ideally contains two 32-bit values that correspond to the
mpubase
The MPU is disabled on system reset. Before enabling the MPU, Intel FPGA
recommends initializing all MPU regions. Enable desired instruction and data regions
by writing each region's attributes to the
in the "MPU Region Read and Write Operations" section of this chapter. You must also
disable unused regions. When using region size, clear
using limit, set the
zero.
Note:
You must enable at least one instruction and one data region, otherwise unpredictable
behavior might occur.
To perform a context switch, use a
config
structure, and then use another
MPU.
Define each region using the pair of
Read and Write Operations" section of this chapter. Repeat this dual
sequence until all desired regions are defined.
Related Information
•
MPU Region Read and Write Operations
•
Memory Regions
3.5.3. Debugger Access
The debugger can access all MPU-related control registers using the normal
and
rdctl
temporarily disabling it.
3.6. Working with ECC
3.6.1. Enabling ECC
The ECC is disabled on system reset. Before enabling the ECC, initialize the Nios II
RAM blocks to avoid spurious ECC errors.
instruction would create unnecessary overhead.
wrctl
and
register formats.
mpuacc
mpubase.BASE
register to disable the MPU, define all MPU regions from the new thread's data
on page 43
instructions. During debugging, the Nios II ignores the MPU, effectively
flushp
and
mpubase
mpuacc.MASK
to a nonzero value and clear
to write a zero to the
wrctl
to write a one to
wrctl
instructions described in the "MPU Region
wrctl
on page 68
instruction or a
wrctl
registers as described
mpuacc
to zero. When
mpuacc.LIMIT
field of the
PE
to enable the
config.PE
instruction
wrctl
wrctl
Nios II Processor Reference Guide
to
69
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