Pc Card Layout Notes; Alternate Bus Master Interface - Intel PXA27 Series Design Manual

6.5.6.3

PC Card Layout Notes

Pull-up resisters shown in
®
Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel
Processor Family Electrical, Mechanical, and Thermal Specification for the A/C timings
information.
Verify all signals are within the domain of their intended use. For example, some PC Card signals
are on VCC_BB and some are on VCC_MEM. One solution is to tie the domains together that are
used in common to a single interface. Another solution is to level shift one domain to equal that of
the other domain being used.
6.5.7

Alternate Bus Master Interface

The PXA27x processor allows an alternate bus master to take control of the external memory bus
and read/write data from the SDRAM in partition 0 (nSDCS<0>). The alternate master is given
control of the bus using a hardware handshake. This handshake is performed through MBREQ and
MBGNT that are invoked through the alternate functions on GPIO pins.
When the alternate master has to take control of the memory bus, it asserts MBREQ. The PXA27x
processor completes any in-progress memory operation and any outstanding SDRAM refresh
cycle. If the PXA27x processor starts a swap operation, the processor does not begin the alternate
bus master mode grant sequence until the operation is complete.
The processor then de-asserts SDCKE and three-states all memory bus pins used with SDRAM
bank 0 (nSDCS0, MA<25:0>, nOE, nWE, nSDRAS, nSDCAS, SDCLK1, MD<31:0>,
DQM<3:0>). All other memory and PC Card pins remain driven. The RDnWR is also three-stated
allowing the alternate bus master to control any transceiver logic that might exist in the design. The
RDnWR pin must still be driven by the alternate bus master:
•
If no transceiver logic exist between the processor and the SDRAM
•
If the RDnWR is used by any devices within the design to prevent any inputs from floating
For the SA-1110 address compatibility mode, the nOE signal is driven after control is passed to the
alternate bus master. To prevent inputs that receive the nOE signal from floating or possible
contention on the data bus, the nOE signal must be driven high by the alternate bus master while
possessing ownership of the bus.
After that, the PXA27x processor asserts MBGNT, the alternate master must start driving all pins
(including SDCLK<1>), and the PXA27x processor must re-assert SDCKE. The grant sequence
and timing are (the Tmem unit of time is the memory clock period):
1. Alternate master asserts MBREQ.
2. The PXA27x processor memory controller performs an SDRAM refresh if SDRAM clocks
and clock enable are turned on.
3. The PXA27x processor memory controller sends an MRS command to the SDRAMs if the
MDCNFG[SA1110_x] bit is turned on to change the SDRAM burst length to 1 instead of 4.
The burst length is changed to 1 for the SA-1110 address compatibility mode.
4. The PXA27x processor de-asserts SDCKE at time (t).
5. The PXA27x processor three-states SDRAM outputs at time (t + 1 x Tmem).
6. The PXA27x processor asserts MBGNT at time (t + 2 x Tmem).
7. Alternate master drives SDRAM signals prior to time (t + 3 x Tmem).
®
Intel PXA27x Processor Design Guide
Figure 6-10 and Figure 6-11
System Memory Interface
must be 10 KΩ or greater in value. Refer to
®
PXA27x
II:6-29