Isa Interface; I/O Recovery Support; Sysclk Generation; Data Byte Swapping (Isa Master Or Dma To Isa Device) - Intel Embedded Intel486 Hardware Reference Manual

EMBEDDED Intel486™ PROCESSOR HARDWARE REFERENCE MANUAL
Host Address/Link, A17–A2 for system controller/ISA bridge, link transfers of data/commands
between the ISA bridge and system controller. These signals are 3-stated after a hard reset.
8.4.5

ISA Interface

The ISA bridge incorporates a fully ISA bus compatible master and slave interface. The ISA
bridge directly drives five ISA slots without external data or address buffers. The ISA interface
also provides byte swap logic, I/O recovery support, wait-state generation, and SYSCLK gener-
ation. The ISA interface supports the following cycle types:
•
CPU or PCI master initiated I/O and memory cycles to the ISA bus.
•
DMA-compatible cycles between main memory and ISA I/O, and between ISA I/O and
ISA memory.
•
ISA refresh cycles initiated by either the ISA bridge or an external ISA master.
•
ISA master-initiated memory cycles to main memory and ISA master-initiated I/O cycles to
the internal ISA bridge registers.
8.4.5.1

I/O Recovery Support

The I/O recovery mechanism in the ISA bridge is used to add additional recovery delay between
the CPU or PCI master initiated 8-bit and 16-bit I/O cycles to the ISA bus. The ISA bridge auto-
matically forces a minimum delay of 3.5 SYSCLKs between back-to-back 8- and 16-bit I/O cy-
cles to the ISA bus. This delay is measured from the rising edge of the I/O command (IOR# or
IOW#) to the falling edge of the next I/O command. If a delay of greater than 3.5 SYSCLKs is
required, the ISA I/O Recovery Timer register can be programmed to increase the delay in incre-
ments of SYSCLKs. No additional delay is inserted for back-to-back I/O sub-cycles generated as
a result of byte assembly or disassembly.
8.4.5.2

SYSCLK Generation

The ISA bridge generates the ISA system clock (SYSCLK). SYSCLK is a divided down version
of HCLKOUT and has a frequency of either 8.00 or 8.33 MHz, depending on the HCLKOUT
frequency.
For CPU or PCI initiated cycles to the ISA bus, SYSCLK is stretched to synchronize BALE fall-
ing to the rising edge of SYSCLK. During CPU or PCI initiated cycles to the ISA bridge, BALE
is normally driven high, synchronized to the rising edge of SYSCLK and then driven low to ini-
tiate the cycle on the ISA bus. However, if the cycle is aborted, BALE remains high and is not
driven low until the next cycle to the ISA bus.
8.4.5.3

Data Byte Swapping (ISA Master or DMA to ISA Device)

The data swap logic is integrated in the ISA bridge. For slaves that reside on the ISA bus, data
swapping is performed if the slave (I/O or memory) and ISA bus master (or DMA) sizes differ
and the upper (odd) byte of data is being accessed. The data swapping direction is determined by
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