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Configuration
Table 7-19. Accessing the Debug Registers (Sheet 2 of 2)
Write DBR0
Read Data Mask/Address Register
(DBR1)
Write DBR1
Read Data Breakpoint Control
Register (DBCON)
Write DBCON
7.2.13
Register 15: Coprocessor Access Register
Register 15: Coprocessor Access Register is selected when opcode_2 = 0 and CRm = 1.
This register controls access rights to all the coprocessors in the system except for CP15 and CP14.
Both CP15 and CP14 can only be accessed in privilege mode. This register is accessed with an
MCR or MRC with the CRm field set to 1.
This register controls access to CP0 on the application processors.
Example 7-1. Disallowing access to CP0
;; The following code clears bit 0 of the CPAR.
;; This will cause the processor to fault if software
;; attempts to access CP0.
Table 7-20. Coprocessor Access Register (Sheet 1 of 2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: 0x0000_0000
Bits
31:16
7-14
Function
LDR R0, =0x3FFE
MCR P15, 0, R0, C15, C1, 0
CPWAIT
Access
Read-unpredictable / Write-as-Zero
opcode_2
CRm
0b000
0b0000
0b000
0b0011
0b000
0b0011
0b000
0b0100
0b000
0b0100
; bit 0 is clear
; move to CPAR
; wait for effect See
C
C
P
P
0 0
1
1
3
2
Reserved - Should be programmed to zero for future
compatibility
Intel® XScale™ Microarchitecture User's Manual
Instruction
MCR p15, 0, Rd, c14, c0, 0
MRC p15, 0, Rd, c14, c3, 0
MCR p15, 0, Rd, c14, c3, 0
MRC p15, 0, Rd, c14, c4, 0
MCR p15, 0, Rd, c14, c4, 0
Section 2.3.3
8
7
6
5
4
3
C
C
C
C
C
C
C
C
C
P
P
P
P
P
P
P
P
P
1
1
9
8
7
6
5
4
3
1
0
Description
2
1
0
C
C
C
P
P
P
2
1
0
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