Intel Core i7 Extreme Edition Manuals

• 3

  Table of Contents
• 9

  Revision History

11

1 Introduction

• 11

  Terminology
  • 11

    Processor Terminology
• 13

  References

15

2 Register Description

• 15

  Register Terminology
• 16

  Platform Configuration Structure
• 17

  Device Mapping
• 17

  Functions Specifically Handled By the Processor
• 18

  Detailed Configuration Space Maps
• 18

  Device 0, Function 0: Generic Non-Core Registers
• 19

  Device 0, Function 1: System Address Decoder Registers
• 20

  Device 2, Function 0: Intel QPI Link 0 Registers
• 21

  Device 2, Function 1: Intel QPI Physical 0 Registers
• 22

  Device 3, Function 0: Integrated Memory Controller Registers
• 23

  Device 3, Function 1: Target Address Decoder Registers
• 24

  Device 4, Function 0: Integrated Memory Controller Channel
• 24

  Control Registers
• 25

  Device 4, Function 1: Integrated Memory Controller Channel
• 25

  Address Registers
• 26

  Device 4, Function 2: Integrated Memory Controller Channel
• 26

  Rank Registers
• 27

  Device 4, Function 3: Integrated Memory Controller Channel
• 27

  Thermal Control Registers
• 28

  Device 5, Function 0: Integrated Memory Controller Channel
• 28

  Control Registers
• 29

  Device 5, Function 1: Integrated Memory Controller Channel
• 29

  Address Registers
• 30

  Device 5, Function 2: Integrated Memory Controller Channel
• 30

  Rank Registers
• 31

  Device 5, Function 3: Integrated Memory Controller Channel
• 31

  Thermal Control Registers
• 32

  Device 6, Function 0: Integrated Memory Controller Channel
• 32

  Control Registers
• 33

  Device 6, Function 1: Integrated Memory Controller Channel
• 33

  Address Registers
• 34

  Device 6, Function 2: Integrated Memory Controller Channel
• 34

  Rank Registers
• 35

  Device 6, Function 3: Integrated Memory Controller Channel
• 35

  Thermal Control Registers
• 36

  PCI Standard Registers
  • 36

    VID - Vendor Identification Register
  • 36

    DID - Device Identification Register
  • 37

    RID - Revision Identification Register
  • 37

    CCR - Class Code Register
  • 38

    HDR - Header Type Register
  • 38

    SID/SVID - Subsystem Identity/Subsystem Vendor Identification Register
  • 39

    PCICMD - Command Register
  • 40

    PCISTS - PCI Status Register
• 41

  SAD - System Address Decoder Registers
  • 41

    Sad_Pam0123
  • 43

    Sad_Pam456
  • 44

    Sad_Hen
  • 44

    Sad_Smram
  • 45

    Sad_Pciexbar
  • 45

    Sad_Dram_Rule_0, Sad_Dram_Rule_1, Sad_Dram_Rule_2
    • 45

      Sad_Dram_Rule_3
    • 45

      Sad_Dram_Rule_4, Sad_Dram_Rule_5
    • 45

      Sad_Dram_Rule_6, Sad_Dram_Rule_7
  • 46

    Sad_Interleave_List_0, Sad_Interleave_List_1
    • 46

      Sad_Interleave_List_2, Sad_Interleave_List_3
    • 46

      Sad_Interleave_List_4, Sad_Interleave_List_5
    • 46

      Sad_Interleave_List_6, Sad_Interleave_List_7
• 47

  Intel QPI Link Registers
  • 47

    Qpi_Qpilcl_L0, Qpi_Qpilcl_L1
• 47

  Integrated Memory Controller Control Registers
  • 47

    Mc_Control
  • 49

    Mc_Status
  • 50

    Mc_Smi_Spare_Dimm_Error_Status
  • 51

    Mc_Smi_Spare_Cntrl
  • 51

    Mc_Reset_Control
  • 52

    Mc_Channel_Mapper
  • 53

    Mc_Max_Dod
  • 54

    Mc_Rd_Crdt_Init
  • 55

    Mc_Crdt_Wr_Thld
  • 55

    Mc_Scrubaddr_Lo
  • 56

    Mc_Scrubaddr_Hi
• 57

  TAD - Target Address Decoder Registers
  • 57

    Tad_Dram_Rule_0, Tad_Dram_Rule_1
    • 57

      Tad_Dram_Rule_2, Tad_Dram_Rule_3
    • 57

      Tad_Dram_Rule_4, Tad_Dram_Rule_5
    • 57

      Tad_Dram_Rule_6, Tad_Dram_Rule_7
• 58

  Tad_Interleave_List_0, Tad_Interleave_List_1
  • 58

    Tad_Interleave_List_2, Tad_Interleave_List_3
  • 58

    Tad_Interleave_List_4, Tad_Interleave_List_5
  • 58

    Tad_Interleave_List_6, Tad_Interleave_List_7

59

Integrated Memory Controller Channel Control Registers

• 59

  Mc_Channel_0_Dimm_Reset_Cmd
  • 59

    Mc_Channel_1_Dimm_Reset_Cmd
  • 59

    Mc_Channel_2_Dimm_Reset_Cmd
• 60

  Mc_Channel_0_Dimm_Init_Cmd
  • 60

    Mc_Channel_1_Dimm_Init_Cmd
  • 60

    Mc_Channel_2_Dimm_Init_Cmd
• 61

  Mc_Channel_0_Dimm_Init_Params
  • 61

    Mc_Channel_1_Dimm_Init_Params
  • 61

    Mc_Channel_2_Dimm_Init_Params
• 62

  Mc_Channel_0_Dimm_Init_Status
  • 62

    Mc_Channel_1_Dimm_Init_Status
  • 62

    Mc_Channel_2_Dimm_Init_Status
• 63

  Mc_Channel_0_Ddr3Cmd
  • 63

    Mc_Channel_1_Ddr3Cmd
  • 63

    Mc_Channel_2_Ddr3Cmd
• 64

  Mc_Channel_0_Refresh_Throttle_Support
  • 64

    Mc_Channel_1_Refresh_Throttle_Support
  • 64

    Mc_Channel_2_Refresh_Throttle_Support
• 64

  Mc_Channel_0_Mrs_Value_0_1
  • 64

    Mc_Channel_1_Mrs_Value_0_1
  • 64

    Mc_Channel_2_Mrs_Value_0_1
• 65

  Mc_Channel_0_Mrs_Value_2
  • 65

    Mc_Channel_1_Mrs_Value_2
  • 65

    Mc_Channel_2_Mrs_Value_2
• 65

  Mc_Channel_0_Rank_Present
  • 65

    Mc_Channel_1_Rank_Present
  • 65

    Mc_Channel_2_Rank_Present
• 66

  Mc_Channel_0_Rank_Timing_A Mc_Channel_1_Rank_Timing_A Mc_Channel_2_Rank_Timing_A
• 69

  Mc_Channel_0_Rank_Timing_B Mc_Channel_1_Rank_Timing_B Mc_Channel_2_Rank_Timing_B
• 70

  Mc_Channel_0_Bank_Timing
  • 70

    Mc_Channel_1_Bank_Timing
  • 70

    Mc_Channel_2_Bank_Timing
• 70

  Mc_Channel_0_Refresh_Timing
  • 70

    Mc_Channel_1_Refresh_Timing
  • 70

    Mc_Channel_2_Refresh_Timing
• 71

  Mc_Channel_0_Cke_Timing Mc_Channel_1_Cke_Timing
  • 71

    Mc_Channel_2_Cke_Timing
• 71

  Mc_Channel_0_Zq_Timing
  • 71

    Mc_Channel_2_Zq_Timing
• 72

  Mc_Channel_0_Rcomp_Params
  • 72

    Mc_Channel_1_Rcomp_Params
  • 72

    Mc_Channel_2_Rcomp_Params
• 72

  Mc_Channel_0_Odt_Params1
  • 72

    Mc_Channel_1_Odt_Params1
  • 72

    Mc_Channel_2_Odt_Params1
• 73

  Mc_Channel_0_Odt_Params2
  • 73

    Mc_Channel_1_Odt_Params2
  • 73

    Mc_Channel_2_Odt_Params2
  • 73

    Mc_Channel_0_Odt_Matrix_Rank_0_3_Rd Mc_Channel_1_Odt_Matrix_Rank_0_3_Rd Mc_Channel_2_Odt_Matrix_Rank_0_3_Rd
  • 74

    Mc_Channel_0_Odt_Matrix_Rank_4_7_Rd Mc_Channel_1_Odt_Matrix_Rank_4_7_Rd Mc_Channel_2_Odt_Matrix_Rank_4_7_Rd
  • 74

    Mc_Channel_0_Odt_Matrix_Rank_0_3_Wr Mc_Channel_1_Odt_Matrix_Rank_0_3_Wr Mc_Channel_2_Odt_Matrix_Rank_0_3_Wr
  • 74

    Mc_Channel_0_Odt_Matrix_Rank_4_7_Wr Mc_Channel_1_Odt_Matrix_Rank_4_7_Wr Mc_Channel_2_Odt_Matrix_Rank_4_7_Wr
  • 75

    Mc_Channel_0_Waq_Params
    • 75

      Mc_Channel_1_Waq_Params
    • 75

      Mc_Channel_2_Waq_Params
  • 76

    Mc_Channel_0_Scheduler_Params
    • 76

      Mc_Channel_1_Scheduler_Params
    • 76

      Mc_Channel_2_Scheduler_Params
  • 76

    Mc_Channel_0_Maintenance_Ops
    • 76

      Mc_Channel_1_Maintenance_Ops
    • 76

      Mc_Channel_2_Maintenance_Ops
  • 77

    Mc_Channel_0_Tx_Bg_Settings
    • 77

      Mc_Channel_1_Tx_Bg_Settings
    • 77

      Mc_Channel_2_Tx_Bg_Settings
  • 77

    Mc_Channel_0_Rx_Bgf_Settings
    • 77

      Mc_Channel_2_Rx_Bgf_Settings
  • 78

    Mc_Channel_0_Ew_Bgf_Settings
    • 78

      Mc_Channel_1_Ew_Bgf_Settings
    • 78

      Mc_Channel_2_Ew_Bgf_Settings
  • 78

    Mc_Channel_0_Ew_Bgf_Offset_Settings
    • 78

      Mc_Channel_1_Ew_Bgf_Offset_Settings
    • 78

      Mc_Channel_2_Ew_Bgf_Offset_Settings
  • 79

    Mc_Channel_0_Pagetable_Params1
    • 79

      Mc_Channel_1_Pagetable_Params1
    • 79

      Mc_Channel_2_Pagetable_Params1
  • 79

    Mc_Channel_0_Pagetable_Params2
    • 79

      Mc_Channel_1_Pagetable_Params2
    • 79

      Mc_Channel_2_Pagetable_Params2
    • 80

      Mc_Tx_Bg_Cmd_Data_Ratio_Settings_Ch2
  • 80

    Mc_Tx_Bg_Cmd_Offset_Settings_Ch0
    • 80

      Mc_Tx_Bg_Cmd_Offset_Settings_Ch1
    • 80

      Mc_Tx_Bg_Cmd_Offset_Settings_Ch2
  • 80

    Mc_Tx_Bg_Data_Offset_Settings_Ch0
    • 80

      Mc_Tx_Bg_Data_Offset_Settings_Ch1
  • 81

    Mc_Channel_0_Addr_Match
    • 81

      Mc_Channel_1_Addr_Match
    • 81

      Mc_Channel_2_Addr_Match
  • 82

    Mc_Channel_0_Ecc_Error_Mask
    • 82

      Mc_Channel_1_Ecc_Error_Mask
    • 82

      Mc_Channel_2_Ecc_Error_Mask
  • 82

    Mc_Channel_0_Ecc_Error_Inject
    • 82

      Mc_Channel_1_Ecc_Error_Inject
    • 82

      Mc_Channel_2_Ecc_Error_Inject

• 3

  Table of Contents
• 6

  Revision History

7

1 About This Manual

• 7

  Content Overview
• 7

  Text Conventions
• 8

  Table 1. Text Conventions
• 9

  Glossary of Terms and Acronyms
• 9

  Table 2. Terms
• 11

  Table 3. Acronyms
• 14

  Related Documents
• 14

  Development Kit Technical Support
  • 14

    Online Support
  • 14

    Additional Technical Support
  • 14

    Table 4. Related Documents

15

2 Getting Started

• 15

  Development Kit Contents
• 16

  Additional Required Hardware Not Included in This Kit
• 16

  Additional Required Software Not Included in This Kit
• 16

  Workspace Preparation
• 17

  System Setup
• 18

  System Power-Up
• 18

  System Power-Down
• 18

  System BIOS
  • 18

    Configuring the BIOS
  • 19

    Programming BIOS Using a Bootable USB Device
• 20

  Instructions to Flash BIOS On SPI

21

3 Development Board Features

• 21

  Block Diagram
• 21

  Mechanical Form Factor
• 21

  Development Board Features Table
• 21

  Figure 1. System Block Diagram
• 22

  Table 5. Development Kit Feature Set Summary
• 23

  Driver Key Features
• 24

  BIOS Key Features
• 24

  System Thermal Management
• 24

  System Features and Operation
  • 25

    Processor
  • 26

    Figure 2. VID Override Circuit
  • 27

    Table 6. Supported DIMM Module Configurations
  • 28

    Table 7. Hardware Straps for Processor PCI Express* Interface Usage
  • 29

    Chipset
  • 30

    Figure 3. Block Diagram of On-Board LAN Implementations
  • 30

    Table 8. PCI Express* Ports
  • 31

    Table 9. Selection of I/O Voltage for the Intel ® High Definition Audio
  • 31

    Table 10. SATA Ports
  • 32

    Table 11. USB Port Mapping
  • 33

    Table 12. Jumper Setting for SPI Programming
  • 34

    Figure 4. BCLK Frequency Select Circuit
  • 35

    Displays
  • 35

    Figure 5. Platform Clocking Circuit
  • 37

    Figure 6. Intel Core™ I7 Processor Based Low-Power Platform Display Interfaces
  • 38

    Debugging Interfaces
  • 38

    Power Management
  • 38

    Power Measurement Support
  • 38

    Table 13. Power Management States
  • 39

    Table 14. Digital Multimeter
  • 39

    Table 15. Power Measurement Resistor for Power Rails
  • 43

    Power Supply Usage and Recommendation

44

4 Development Board Physical Hardware Reference

• 44

  Primary Features
• 44

  Figure 7. Component Locations - Top View
• 45

  Figure 8. Component Locations - Bottom View
• 45

  Table 16. Component Location
• 47

  Connectors
  • 47

    Table 17. Connectors On the Motherboard
  • 48

    Back Panel Connectors
• 48

  Configuration Settings
• 48

  Figure 9. Back Panel Connector Locations
• 48

  Table 18. Back Panel Connectors
• 48

  Table 19. Configuration Jumper/Switches Settings
• 51

  Power On and Reset Push Buttons
• 52

  Leds
• 52

  Table 20. Power-On and Reset Push Buttons
• 52

  Table 21. Development Lit Leds
• 53

  Other Headers
  • 53

    H8 Programming Header
  • 53

    Expansion Slots and Sockets
  • 53

    Table 22. H8 Programming Jumpers
  • 54

    Table 23. Expansion Slots and Sockets
  • 54

    Table 24. Fan Connector (J4C1)
  • 54

    Table 25. Front Panel Connector
  • 55

    Table 26. Edp Support Connector
  • 55

    Table 27. SATA Port 0 'Direct Connect' Connector Pinout (J8J1)
  • 56

    Table 28. SATA Ports 1 and 2/Esata Ports 3 and 4 Pinout (J7G2, J7G1, J6J1, J7J1)
  • 56

    Table 29. SATA Power Connector (J6H1)
  • 56

    Table 30. SPI Programming Header (J8E1)
  • 57

    Table 31. HAD Header for MDC Interposer (J9E4)
  • 57

    Table 32.HAD Header for MDC Interposer (J9E7)
  • 58

    Table 33. HAD Header for External HDMI Support (J8F1)
  • 58

    Table 34. LED Header (J8G3)
  • 59

    Table 35. Descriptor Security Override (J8F4)
  • 59

    Table 36. Controller Link Header (J8G2)
  • 60

    Table 37. TPM Header/Port 80 Add-In-Card Header (J9A1)
  • 60

    Table 38. LPC Hot Docking (J9E5)
  • 61

    Table 39. LPC Side Band Header (J9G2)

63

5 Daughter and Plug-In Cards

• 63

  Pcie* Add-In Card
• 63

  PCI Expansion Card
• 63

  Figure 10. Pcie* Add-In Card
• 64

  Port 80-83 Add-In Card
• 64

  Figure 11. PCI Expansion Card
• 64

  Figure 12. Port 80-83 Interposer Card
• 65

  Figure 13. Block Diagram of Port 80-83 Add-In Card
• 65

  Table 40. Jumper Settings for Port 80-80 Card
• 65

  Dev Kit Manual 5

66

6 Heatsink Installation Instructions

• 66

  Figure 14. Disassembled Fan/Heatsink Assembly
• 67

  Figure 15. Bottom View of the CRB with Backplate in Place
• 68

  Figure 16. Top View of Board with Pins Installed, Through the Board, and Into the Backplate (Backplate Not Visible)
• 69

  Figure 17. Applying Thermal Grease to the Top of Processor Package
• 70

  Figure 18. Squeeze Activation Arm Downward, Toward the Board
• 70

  323094 Dev Kit Manual
  • 71

    Compression Assembly Handle
  • 71

    Figure 19. Installing Fan/Heatsink
  • 72

    Figure 20. Fan/Heatsink Power Plugged Into Board
  • 73

    Figure 21. Completed Intel ® Core™ I7 Processor CRB with Fan/Heatsink