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Core i7 Extreme Edition
Intel Core i7 Extreme Edition Manuals
Manuals and User Guides for Intel Core i7 Extreme Edition. We have
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Intel Core i7 Extreme Edition manuals available for free PDF download: Datasheet, Installation Instructions Manual, User Manual
Intel Core i7 Extreme Edition Datasheet (98 pages)
Data Sheet
Brand:
Intel
| Category:
Computer Hardware
| Size: 1.24 MB
Table of Contents
Table of Contents
3
Revision History
9
1 Introduction
11
Terminology
11
Processor Terminology
11
References
13
2 Register Description
15
Register Terminology
15
Platform Configuration Structure
16
Device Mapping
17
Functions Specifically Handled by the Processor
17
Detailed Configuration Space Maps
18
Device 0, Function 0: Generic Non-Core Registers
18
Device 0, Function 1: System Address Decoder Registers
19
Device 2, Function 0: Intel QPI Link 0 Registers
20
Device 2, Function 1: Intel QPI Physical 0 Registers
21
Device 3, Function 0: Integrated Memory Controller Registers
22
Device 3, Function 1: Target Address Decoder Registers
23
Device 4, Function 0: Integrated Memory Controller Channel
24
Control Registers
24
Device 4, Function 1: Integrated Memory Controller Channel
25
Address Registers
25
Device 4, Function 2: Integrated Memory Controller Channel
26
Rank Registers
26
Device 4, Function 3: Integrated Memory Controller Channel
27
Thermal Control Registers
27
Device 5, Function 0: Integrated Memory Controller Channel
28
Control Registers
28
Device 5, Function 1: Integrated Memory Controller Channel
29
Address Registers
29
Device 5, Function 2: Integrated Memory Controller Channel
30
Rank Registers
30
Device 5, Function 3: Integrated Memory Controller Channel
31
Thermal Control Registers
31
Device 6, Function 0: Integrated Memory Controller Channel
32
Control Registers
32
Device 6, Function 1: Integrated Memory Controller Channel
33
Address Registers
33
Device 6, Function 2: Integrated Memory Controller Channel
34
Rank Registers
34
Device 6, Function 3: Integrated Memory Controller Channel
35
Thermal Control Registers
35
PCI Standard Registers
36
VID - Vendor Identification Register
36
DID - Device Identification Register
36
RID - Revision Identification Register
37
CCR - Class Code Register
37
HDR - Header Type Register
38
SID/SVID - Subsystem Identity/Subsystem Vendor Identification Register
38
PCICMD - Command Register
39
PCISTS - PCI Status Register
40
SAD - System Address Decoder Registers
41
Sad_Pam0123
41
Sad_Pam456
43
Sad_Hen
44
Sad_Smram
44
Sad_Pciexbar
45
Sad_Dram_Rule_0, Sad_Dram_Rule_1, Sad_Dram_Rule_2
45
Sad_Dram_Rule_3
45
Sad_Dram_Rule_4, Sad_Dram_Rule_5
45
Sad_Dram_Rule_6, Sad_Dram_Rule_7
45
Sad_Interleave_List_0, Sad_Interleave_List_1
46
Sad_Interleave_List_2, Sad_Interleave_List_3
46
Sad_Interleave_List_4, Sad_Interleave_List_5
46
Sad_Interleave_List_6, Sad_Interleave_List_7
46
Intel QPI Link Registers
47
Qpi_Qpilcl_L0, Qpi_Qpilcl_L1
47
Integrated Memory Controller Control Registers
47
Mc_Control
47
Mc_Status
49
Mc_Smi_Spare_Dimm_Error_Status
50
Mc_Smi_Spare_Cntrl
51
Mc_Reset_Control
51
Mc_Channel_Mapper
52
Mc_Max_Dod
53
Mc_Rd_Crdt_Init
54
Mc_Crdt_Wr_Thld
55
Mc_Scrubaddr_Lo
55
Mc_Scrubaddr_Hi
56
TAD - Target Address Decoder Registers
57
Tad_Dram_Rule_0, Tad_Dram_Rule_1
57
Tad_Dram_Rule_2, Tad_Dram_Rule_3
57
Tad_Dram_Rule_4, Tad_Dram_Rule_5
57
Tad_Dram_Rule_6, Tad_Dram_Rule_7
57
Tad_Interleave_List_0, Tad_Interleave_List_1
58
Tad_Interleave_List_2, Tad_Interleave_List_3
58
Tad_Interleave_List_4, Tad_Interleave_List_5
58
Tad_Interleave_List_6, Tad_Interleave_List_7
58
Integrated Memory Controller Channel Control Registers
59
Mc_Channel_0_Dimm_Reset_Cmd
59
Mc_Channel_1_Dimm_Reset_Cmd
59
Mc_Channel_2_Dimm_Reset_Cmd
59
Mc_Channel_0_Dimm_Init_Cmd
60
Mc_Channel_1_Dimm_Init_Cmd
60
Mc_Channel_2_Dimm_Init_Cmd
60
Mc_Channel_0_Dimm_Init_Params
61
Mc_Channel_1_Dimm_Init_Params
61
Mc_Channel_2_Dimm_Init_Params
61
Mc_Channel_0_Dimm_Init_Status
62
Mc_Channel_1_Dimm_Init_Status
62
Mc_Channel_2_Dimm_Init_Status
62
Mc_Channel_0_Ddr3Cmd
63
Mc_Channel_1_Ddr3Cmd
63
Mc_Channel_2_Ddr3Cmd
63
Mc_Channel_0_Refresh_Throttle_Support
64
Mc_Channel_1_Refresh_Throttle_Support
64
Mc_Channel_2_Refresh_Throttle_Support
64
Mc_Channel_0_Mrs_Value_0_1
64
Mc_Channel_1_Mrs_Value_0_1
64
Mc_Channel_2_Mrs_Value_0_1
64
Mc_Channel_0_Mrs_Value_2
65
Mc_Channel_1_Mrs_Value_2
65
Mc_Channel_2_Mrs_Value_2
65
Mc_Channel_0_Rank_Present
65
Mc_Channel_1_Rank_Present
65
Mc_Channel_2_Rank_Present
65
Mc_Channel_0_Rank_Timing_A Mc_Channel_1_Rank_Timing_A Mc_Channel_2_Rank_Timing_A
66
Mc_Channel_0_Rank_Timing_B Mc_Channel_1_Rank_Timing_B Mc_Channel_2_Rank_Timing_B
69
Mc_Channel_0_Bank_Timing
70
Mc_Channel_1_Bank_Timing
70
Mc_Channel_2_Bank_Timing
70
Mc_Channel_0_Refresh_Timing
70
Mc_Channel_1_Refresh_Timing
70
Mc_Channel_2_Refresh_Timing
70
Mc_Channel_0_Cke_Timing Mc_Channel_1_Cke_Timing
71
Mc_Channel_2_Cke_Timing
71
Mc_Channel_0_Zq_Timing
71
Mc_Channel_2_Zq_Timing
71
Mc_Channel_0_Rcomp_Params
72
Mc_Channel_1_Rcomp_Params
72
Mc_Channel_2_Rcomp_Params
72
Mc_Channel_0_Odt_Params1
72
Mc_Channel_1_Odt_Params1
72
Mc_Channel_2_Odt_Params1
72
Mc_Channel_0_Odt_Params2
73
Mc_Channel_1_Odt_Params2
73
Mc_Channel_2_Odt_Params2
73
Mc_Channel_0_Odt_Matrix_Rank_0_3_Rd Mc_Channel_1_Odt_Matrix_Rank_0_3_Rd Mc_Channel_2_Odt_Matrix_Rank_0_3_Rd
73
Mc_Channel_0_Odt_Matrix_Rank_0_3_Wr Mc_Channel_1_Odt_Matrix_Rank_0_3_Wr Mc_Channel_2_Odt_Matrix_Rank_0_3_Wr
74
Mc_Channel_0_Odt_Matrix_Rank_4_7_Rd Mc_Channel_1_Odt_Matrix_Rank_4_7_Rd Mc_Channel_2_Odt_Matrix_Rank_4_7_Rd
74
Mc_Channel_0_Odt_Matrix_Rank_4_7_Wr Mc_Channel_1_Odt_Matrix_Rank_4_7_Wr Mc_Channel_2_Odt_Matrix_Rank_4_7_Wr
74
Mc_Channel_0_Waq_Params
75
Mc_Channel_1_Waq_Params
75
Mc_Channel_2_Waq_Params
75
Mc_Channel_0_Maintenance_Ops
76
Mc_Channel_0_Scheduler_Params
76
Mc_Channel_1_Maintenance_Ops
76
Mc_Channel_1_Scheduler_Params
76
Mc_Channel_2_Maintenance_Ops
76
Mc_Channel_2_Scheduler_Params
76
Mc_Channel_0_Rx_Bgf_Settings
77
Mc_Channel_0_Tx_Bg_Settings
77
Mc_Channel_1_Tx_Bg_Settings
77
Mc_Channel_2_Rx_Bgf_Settings
77
Mc_Channel_2_Tx_Bg_Settings
77
Mc_Channel_0_Ew_Bgf_Offset_Settings
78
Mc_Channel_0_Ew_Bgf_Settings
78
Mc_Channel_0_Round_Trip_Latency
78
Mc_Channel_1_Ew_Bgf_Offset_Settings
78
Mc_Channel_1_Ew_Bgf_Settings
78
Mc_Channel_1_Round_Trip_Latency
78
Mc_Channel_2_Ew_Bgf_Offset_Settings
78
Mc_Channel_2_Ew_Bgf_Settings
78
Mc_Channel_2_Round_Trip_Latency
78
Mc_Channel_0_Pagetable_Params1
79
Mc_Channel_0_Pagetable_Params2
79
Mc_Channel_1_Pagetable_Params1
79
Mc_Channel_1_Pagetable_Params2
79
Mc_Channel_2_Pagetable_Params1
79
Mc_Channel_2_Pagetable_Params2
79
Mc_Tx_Bg_Cmd_Data_Ratio_Settings_Ch2
80
Mc_Tx_Bg_Cmd_Offset_Settings_Ch0
80
Mc_Tx_Bg_Cmd_Offset_Settings_Ch1
80
Mc_Tx_Bg_Cmd_Offset_Settings_Ch2
80
Mc_Tx_Bg_Data_Offset_Settings_Ch0
80
Mc_Tx_Bg_Data_Offset_Settings_Ch1
80
Mc_Tx_Bg_Data_Offset_Settings_Ch2
80
Mc_Channel_0_Addr_Match
81
Mc_Channel_1_Addr_Match
81
Mc_Channel_2_Addr_Match
81
Mc_Channel_0_Ecc_Error_Inject
82
Mc_Channel_0_Ecc_Error_Mask
82
Mc_Channel_1_Ecc_Error_Inject
82
Mc_Channel_1_Ecc_Error_Mask
82
Mc_Channel_2_Ecc_Error_Inject
82
Mc_Channel_2_Ecc_Error_Mask
82
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Intel Core i7 Extreme Edition Datasheet (102 pages)
Brand:
Intel
| Category:
Computer Hardware
| Size: 0.85 MB
Table of Contents
Table of Contents
3
Revision History
8
1 Introduction
9
High-Level View of Processor Interfaces
9
Terminology
10
References
11
2 Electrical Specifications
13
Intel® QPI Differential Signaling
13
Power and Ground Lands
13
Decoupling Guidelines
13
Active ODT for a Differential Link Example
13
VCC, VTTA, VTTD, VDDQ Decoupling
14
Processor Clocking (BCLK_DP, BCLK_DN)
14
PLL Power Supply
14
Voltage Identification (VID)
14
Voltage Identification Definition
15
Reserved or Unused Signals
17
Market Segment Selection Truth Table for MS_ID[2:0]
17
Signal Groups
18
Test Access Port (TAP) Connection
19
Signals with ODT
19
Platform Environmental Control Interface (PECI) DC Specifications
20
DC Characteristics
20
PECI DC Electrical Limits
20
Input Device Hysteresis
21
Absolute Maximum and Minimum Ratings
21
Processor DC Specifications
22
Processor Absolute Minimum and Maximum Ratings
22
DC Voltage and Current Specification
23
Voltage and Current Specifications
23
VCC Static and Transient Tolerance Load Lines
25
VTT Static and Transient Tolerance Load Line
27
VTT Static and Transient Tolerance
27
DDR3 Signal Group DC Specifications
27
RESET# Signal DC Specifications
28
TAP Signal Group DC Specifications
28
PWRGOOD Signal Group DC Specifications
28
VCC Overshoot Specification
29
Control Sideband Signal Group DC Specifications
29
Die Voltage Validation
30
VCC Overshoot Example Waveform
30
3 Package Mechanical Specifications
31
Package Mechanical Drawing
31
Processor Package Assembly Sketch
31
Processor Package Drawing (Sheet 1 of 2)
32
Processor Package Drawing (Sheet 2 of 2)
33
Processor Component Keep-Out Zones
34
Package Loading Specifications
34
Package Handling Guidelines
34
Package Insertion Specifications
34
Processor Loading Specifications
34
Processor Mass Specification
35
Processor Materials
35
Processor Markings
35
Processor Top-Side Markings
35
Processor Land Coordinates
36
Processor Land Coordinates and Quadrants (Bottom View)
36
4 Land Listing
37
Land Listing by Land Name
37
Land Listing by Land Number
55
5 Signal Definitions
73
6 Thermal Specifications
77
Package Thermal Specifications
77
Processor Thermal Specifications
78
Processor Thermal Profile
79
Thermal Metrology
81
Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location
81
Processor Thermal Features
82
Processor Temperature
82
Adaptive Thermal Monitor
82
Frequency and Voltage Ordering
83
THERMTRIP# Signal
85
Platform Environment Control Interface (PECI)
85
Introduction
85
Fan Speed Control with Digital Thermal Sensor
86
PECI Specifications
87
Supported PECI Command Functions and Codes
87
Gettemp0() Error Codes
87
Storage Conditions Specifications
88
Storage Condition Ratings
88
7 Features
89
Power-On Configuration (POC)
89
Clock Control and Low Power States
89
Power on Configuration Signal Options
89
Thread and Core Power State Descriptions
90
Power States
90
Coordination of Thread Power States at the Core Level
90
Package Power State Descriptions
91
Sleep States
92
ACPI P-States (Intel Turbo Boost Technology)
92
Processor S-States
92
Enhanced Intel Speedstep Technology
93
8 Boxed Processor Specifications
95
Introduction
95
Mechanical Representation of the Boxed Processor
95
Mechanical Specifications
96
Boxed Processor Cooling Solution Dimensions
96
Space Requirements for the Boxed Processor (Side View)
96
Space Requirements for the Boxed Processor (Top View)
97
Space Requirements for the Boxed Processor (Overall View)
97
Boxed Processor Fan Heatsink Weight
98
Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly
98
Electrical Requirements
98
Fan Heatsink Power Supply
98
Boxed Processor Fan Heatsink Power Cable Connector Description
98
Thermal Specifications
99
Boxed Processor Cooling Requirements
99
Baseboard Power Header Placement Relative to Processor Socket
99
Fan Heatsink Power and Signal Specifications
99
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top View)
100
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side View)
100
Variable Speed Fan
101
Boxed Processor Fan Heatsink Set Points
101
Fan Heatsink Power and Signal Specifications
101
Intel Core i7 Extreme Edition User Manual (73 pages)
QM57 Express Chipset
Brand:
Intel
| Category:
Computer Hardware
| Size: 4.14 MB
Table of Contents
Table of Contents
3
Revision History
6
1 About this Manual
7
Content Overview
7
Text Conventions
7
Table 1. Text Conventions
8
Glossary of Terms and Acronyms
9
Table 2. Terms
9
Table 3. Acronyms
11
Related Documents
14
Development Kit Technical Support
14
Online Support
14
Additional Technical Support
14
Table 4. Related Documents
14
2 Getting Started
15
Development Kit Contents
15
Additional Required Hardware Not Included in this Kit
16
Additional Required Software Not Included in this Kit
16
Workspace Preparation
16
System Setup
17
System Power-Up
18
System Power-Down
18
System BIOS
18
Configuring the BIOS
18
Programming BIOS Using a Bootable USB Device
19
Instructions to Flash BIOS on SPI
20
3 Development Board Features
21
Block Diagram
21
Mechanical Form Factor
21
Development Board Features Table
21
Figure 1. System Block Diagram
21
Table 5. Development Kit Feature Set Summary
22
Driver Key Features
23
BIOS Key Features
24
System Thermal Management
24
System Features and Operation
24
Processor
25
Figure 2. VID Override Circuit
26
Table 6. Supported DIMM Module Configurations
27
Table 7. Hardware Straps for Processor PCI Express* Interface Usage
28
Chipset
29
Figure 3. Block Diagram of On-Board LAN Implementations
30
Table 8. PCI Express* Ports
30
Table 9. Selection of I/O Voltage for the Intel ® High Definition Audio
31
Table 10. SATA Ports
31
Table 11. USB Port Mapping
32
Table 12. Jumper Setting for SPI Programming
33
Figure 4. BCLK Frequency Select Circuit
34
Displays
35
Figure 5. Platform Clocking Circuit
35
Figure 6. Intel Core™ I7 Processor Based Low-Power Platform Display Interfaces
37
Debugging Interfaces
38
Power Management
38
Power Measurement Support
38
Table 13. Power Management States
38
Table 14. Digital Multimeter
39
Table 15. Power Measurement Resistor for Power Rails
39
Power Supply Usage and Recommendation
43
4 Development Board Physical Hardware Reference
44
Primary Features
44
Figure 7. Component Locations - Top View
44
Figure 8. Component Locations - Bottom View
45
Table 16. Component Location
45
Connectors
47
Table 17. Connectors on the Motherboard
47
Back Panel Connectors
48
Configuration Settings
48
Figure 9. Back Panel Connector Locations
48
Table 18. Back Panel Connectors
48
Table 19. Configuration Jumper/Switches Settings
48
Power on and Reset Push Buttons
51
Leds
52
Table 20. Power-On and Reset Push Buttons
52
Table 21. Development Lit Leds
52
Other Headers
53
H8 Programming Header
53
Expansion Slots and Sockets
53
Table 22. H8 Programming Jumpers
53
Table 23. Expansion Slots and Sockets
54
Table 24. Fan Connector (J4C1)
54
Table 25. Front Panel Connector
54
Table 26. Edp Support Connector
55
Table 27. SATA Port 0 'Direct Connect' Connector Pinout (J8J1)
55
Table 28. SATA Ports 1 and 2/Esata Ports 3 and 4 Pinout (J7G2, J7G1, J6J1, J7J1)
56
Table 29. SATA Power Connector (J6H1)
56
Table 30. SPI Programming Header (J8E1)
56
Table 31. HAD Header for MDC Interposer (J9E4)
57
Table 32.HAD Header for MDC Interposer (J9E7)
57
Table 33. HAD Header for External HDMI Support (J8F1)
58
Table 34. LED Header (J8G3)
58
Table 35. Descriptor Security Override (J8F4)
59
Table 36. Controller Link Header (J8G2)
59
Table 37. TPM Header/Port 80 Add-In-Card Header (J9A1)
60
Table 38. LPC Hot Docking (J9E5)
60
Table 39. LPC Side Band Header (J9G2)
61
5 Daughter and Plug-In Cards
63
Pcie* Add-In Card
63
PCI Expansion Card
63
Figure 10. Pcie* Add-In Card
63
Port 80-83 Add-In Card
64
Figure 11. PCI Expansion Card
64
Figure 12. Port 80-83 Interposer Card
64
Figure 13. Block Diagram of Port 80-83 Add-In Card
65
Table 40. Jumper Settings for Port 80-80 Card
65
Dev Kit Manual 5
65
6 Heatsink Installation Instructions
66
Figure 14. Disassembled Fan/Heatsink Assembly
66
Figure 15. Bottom View of the CRB with Backplate in Place
67
Figure 16. Top View of Board with Pins Installed, through the Board, and into the Backplate (Backplate Not Visible)
68
Figure 17. Applying Thermal Grease to the Top of Processor Package
69
Figure 18. Squeeze Activation Arm Downward, Toward the Board
70
323094 Dev Kit Manual
70
Compression Assembly Handle
71
Figure 19. Installing Fan/Heatsink
71
Figure 20. Fan/Heatsink Power Plugged into Board
72
Figure 21. Completed Intel ® Core™ I7 Processor CRB with Fan/Heatsink
73
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Intel Core i7 Extreme Edition Installation Instructions Manual (80 pages)
Brand:
Intel
| Category:
Computer Hardware
| Size: 4.61 MB
Table of Contents
Boxed Intel Processor Installation Instructions
9
Extent of Limited Warranty
27
How to Obtain Warranty Service
28
Warranty Limitations and Exclusions
29
Limitations of Liability
29
Garantie Limitée
30
Beschränkte Gewährleistung
34
Garantía Limitada
38
Como Obter O Serviço de Garantia
43
Garanzia Limitata
45
Ograniczona Gwarancja
49
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