Expansion Card Connector Topology; Pci Express* Expansion Card Connector Topology - Intel Quark SoC X1000 Design Manual

4.3.1

Expansion Card Connector Topology

The Design Guide recommendations are based on surface mount connectors that meet
the insertion loss and return loss characteristics as specified in PCI Express* CEM 2.0
Specification. These guidelines include all trace routing on the board and the breakout
region.
• For PCI Express* interface composed of x1 links, it is most practical to route the TX
signals and RX signals of each link next to each other on the same layer following
interleaved routing.
• The PCI Express* expansion card topology simulations showed the lowest margins
compared to other PCI Express* interfaces. Additional simulation may be required
for different specific design scenarios.
• For a 4 layer board only microstrip (MS) is applicable.
• AC coupling capacitors for PET pair on the motherboard are recommended to be
placed very close to the expansion connector. Avoid placing AC caps at the center of
the motherboard main route.
• Refer to
Figure 23.

PCI Express* Expansion Card Connector Topology

SoC
P1 L0
+
TX
-
P1 L0
P1 L0
+
RX
-
P1 L0
®
Intel Quark™ SoC X1000
PDG
44
Section 10.3.1for PCIe* clock guidelines.
L1 L2
t t
t
AC Coupling Caps
t
L1 L2
t t
L1 L2
r r
r
r
L1 L2
r r
®
Intel Quark™ SoC X1000—PCI Express* Design Guidelines
Connector
L3
t
L4
t
L4
t
L3
t
PCIe*
Device
Express
Card
June 2014
Order Number: 330258-002US