Sdram Power Failure Guidelines; System Assumptions; External Logic Required For Power Failure; External Power Failure State Machine - Intel i960 Design Manual

4.2.3

SDRAM Power Failure Guidelines

SDRAM technology provides a simple way of enabling data preservation through the self-refresh
command. When the memory controller issues this command, the SDRAM refreshes itself
autonomously with internal logic and timers.
The SDRAM device remains in self-refresh mode as long as:
•
The device continues to be powered.
•
SCKE is held low until the memory controller is ready to control the SDRAM once again.
The board design should ensure power to the SDRAM subsystem with an adequate battery backup
and a reliable method for switching between system power and battery power. The memory
controller is responsible for deasserting SCKE[1:0] when issuing the self-refresh command
however, while power gradually drops, SCKE[1:0]
of V powering the
cc
4.2.4

System Assumptions

The board design should ensure that P_RST# is asserted to the
1 ms of reliable power is remaining. This is required so that the memory controller can execute its
power-failure state machine in response to the assertion of P_RST#.
4.2.5

External Logic Required for Power Failure

Refer to Figure
implementations may vary. This state machine can be implemented in a programmable logic device
illustrated in
Figure 4-12. External Power Failure State Machine
Design Guide
RM/RN I/O processor.
for a state machine of the external logic required for power failure mode. Actual
Figure 4-13.
PULLCKE = 1
Intel® i960® RM/RN I/O Processor
®
Intel 80960RM/RN Processor Memory Subsystem
MUST remain deasserted regardless of the state
RM/RN I/O processor
*
SCKE
out
PULLCKE = 0
P_RST#
when at least
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