Ma-Message Address Register; Md-Message Data Register; Peg_Capl-Pci Express-G Capability List Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.6.31 MA—Message Address Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
31:2
1:0
2.6.32 MD—Message Data Register
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
15:0
2.6.33 PEG_CAPL—PCI Express-G Capability List Register
Enumerates the PCI Express capability structure.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
15:8
7:0
Datasheet, Volume 2
0/1/0–2/PCI
94–97h
00000000h
RW, RO
32 bits
Reset RST/
Attr
Value PWR
00000000
RW Uncore
h
RO 00b Uncore
0/1/0–2/PCI
98–99h
0000h
RW
16 bits
Reset RST/
Attr
Value PWR
RW 0000h Uncore
0/1/0–2/PCI
A0–A1h
0010h
RO
16 bits
Reset RST/
Attr
Value PWR
RO 00h Uncore
RO 10h Uncore
Description
Message Address (MA)
Used by system software to assign an MSI address to the device.
The device handles an MSI by writing the padded contents of the
MD register to this address.
Force DWord Align (FDWA)
Hardwired to 0 so that addresses assigned by system software are
always aligned on a dword address boundary.
Description
Message Data (MD)
Base message data pattern assigned by system software and used
to handle an MSI from the device.
When the device must generate an interrupt request, it writes a
32-bit value to the memory address specified in the MA register.
The upper 16 bits are always set to 0. The lower 16 bits are
supplied by this register.
Description
Pointer to Next Capability (PNC)
This value terminates the capabilities list. The Virtual Channel
capability and any other PCI Express specific capabilities that are
reported using this mechanism are in a separate capabilities list
located entirely within PCI Express Extended Configuration Space.
Capability ID (CID)
Identifies this linked list item (capability structure) as being for PCI
Express registers.
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