ST STM32F207 Series Reference Manual page 732

Serial peripheral interface (SPI)
Bit 7 PCMSYNC: PCM frame synchronization
0: Short frame synchronization
1: Long frame synchronization
Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used)
It is not used in SPI mode.
Bit 6 Reserved: forced at 0 by hardware
Bits 5:4 I2SSTD: I2S standard selection
2
00: I S Philips standard.
01: MSB justified standard (left justified)
10: LSB justified standard (right justified)
11: PCM standard
For more details on I
in SPI mode.
Note: For correct operation, these bits should be configured when the I
Bit 3 CKPOL: Steady state clock polarity
2
0: I S clock steady state is low level
2
1: I S clock steady state is high level
Note: For correct operation, this bit should be configured when the I
This bit is not used in SPI mode
Bits 2:1 DATLEN: Data length to be transferred
00: 16-bit data length
01: 24-bit data length
10: 32-bit data length
11: Not allowed
Note: For correct operation, these bits should be configured when the I
This bit is not used in SPI mode.
Bit 0 CHLEN: Channel length (number of bits per audio channel)
0: 16-bit wide
1: 32-bit wide
The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to
32-bit by hardware whatever the value filled in. Not used in SPI mode.
Note: For correct operation, this bit should be configured when the I
732/1381
2
Section 25.4.2: Supported audio protocols
S standards, refer to
RM0033 Rev 9
RM0033
. Not used
2
S is disabled.
2
S is disabled.
2
S is disabled.
2
S is disabled.