ST STM32F207 Series Reference Manual page 889

RM0033
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TDES0: Transmit descriptor Word0
The application software has to program the control bits [30:26]+[23:20] plus the OWN
bit [31] during descriptor initialization. When the DMA updates the descriptor (or writes
it back), it resets all the control bits plus the OWN bit, and reports only the status bits.
31 30
OWN IC
rw rw
15 14
ES JT
rw rw
Bit 31 OWN: Own bit
Bit 30 IC: Interrupt on completion
Bit 29 LS: Last segment
Bit 28 FS: First segment
Bit 27 DC: Disable CRC
Bit 26 DP: Disable pad
Bit 25 TTSE: Transmit time stamp enable
Bit 24 Reserved, must be kept at reset value.
Bits 23:22 CIC: Checksum insertion control
These bits control the checksum calculation and insertion. Bit encoding is as shown below:
Ethernet (ETH): media access control (MAC) with DMA controller
29 28 27
LS FS DC DP
rw rw rw
13 12 11
FF IPE LCA NC
rw rw rw
When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it
indicates that the descriptor is owned by the CPU. The DMA clears this bit either when it
completes the frame transmission or when the buffers allocated in the descriptor are read
completely. The ownership bit of the frame's first descriptor must be set after all subsequent
descriptors belonging to the same frame have been set.
When set, this bit sets the Transmit Interrupt (ETH_DMASR[0]) after the present frame has
been transmitted.
When set, this bit indicates that the buffer contains the last segment of the frame.
When set, this bit indicates that the buffer contains the first segment of a frame.
When this bit is set, the MAC does not append a cyclic redundancy check (CRC) to the end
of the transmitted frame. This is valid only when the first segment (TDES0[28]) is set.
When set, the MAC does not automatically add padding to a frame shorter than 64 bytes.
When this bit is reset, the DMA automatically adds padding and CRC to a frame shorter than
64 bytes, and the CRC field is added despite the state of the DC (TDES0[27]) bit. This is
valid only when the first segment (TDES0[28]) is set.
When TTSE is set and when TSE is set (ETH_PTPTSCR bit 0), IEEE1588 hardware time
stamping is activated for the transmit frame described by the descriptor. This field is only valid
when the First segment control bit (TDES0[28]) is set.
00: Checksum Insertion disabled
01: Only IP header checksum calculation and insertion are enabled
10: IP header checksum and payload checksum calculation and insertion are enabled, but
pseudo-header checksum is not calculated in hardware
11: IP Header checksum and payload checksum calculation and insertion are enabled, and
pseudo-header checksum is calculated in hardware.
26 25 24 23
TTSE CIC
Res
rw rw rw
10 9 8 7
LCO EC VF
rw rw rw rw
RM0033 Rev 9
22 21 20 19
TER TCH
Res.
rw rw rw
6 5 4 3
CC
rw rw rw rw
18 17 16
TTSS IHE
rw rw
2 1 0
ED UF DB
rw rw rw
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