ST STM32F207 Series Reference Manual page 71

RM0033
Exiting low-power mode
The MCU exits from Sleep and Stop modes low-power mode depending on the way the low-
power mode was entered:
•
If the WFI instruction or Return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
•
If the WFE instruction is used to enter the low-power mode, the MCU exits the low-
power mode as soon as an event occurs. The wakeup event can be generated either
by:
–
–
The MCU exits from Standby low-power mode through an external reset (NRST pin), an
IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see
Figure 215: RTC block
After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).
NVIC IRQ interrupt:
When SEVONPEND = 0 in the Cortex
an interrupt in the peripheral control register and in the NVIC. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared. Only NVIC interrupts with sufficient priority will wakeup and interrupt the
MCU.
When SEVONPEND = 1 in the Cortex
an interrupt in the peripheral control register and optionally in the NVIC. When the
MCU resumes from WFE, the peripheral interrupt pending bit and when enabled
the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending
register) have to be cleared. All NVIC interrupts will wakeup the MCU, even the
disabled ones.Only enabled NVIC interrupts with sufficient priority will wakeup and
interrupt the MCU.
Event
This is done by configuring a EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or
the NVIC IRQ channel pending bit as the pending bits corresponding to the event
line is not set. It may be necessary to clear the interrupt flag in the peripheral.
diagram).
®
-M3 System Control register: by enabling
®
-M3 System Control register: by enabling
RM0033 Rev 9
Power control (PWR)
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