ST STM32F207 Series Reference Manual page 726

Serial peripheral interface (SPI)
Bit 10 RXONLY: Receive only
Note: This bit is not used in I
Bit 9 SSM: Software slave management
Note: This bit is not used in I
Bit 8 SSI: Internal slave select
Note: This bit is not used in I
Bit 7 LSBFIRST: Frame format
Note: This bit should not be changed when communication is ongoing.
Bit 6 SPE: SPI enable
Note: This bit is not used in I
Bits 5:3 BR[2:0]: Baud rate control
Note: These bits should not be changed when communication is ongoing.
Bit 2 MSTR: Master selection
Note: This bit should not be changed when communication is ongoing.
726/1381
This bit combined with the BIDImode bit selects the direction of transfer in 2-line
unidirectional mode. This bit is also useful in a multislave system in which this particular
slave is not accessed, the output from the accessed slave is not corrupted.
0: Full duplex (Transmit and receive)
1: Output disabled (Receive-only mode)
When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the
NSS pin and the IO value of the NSS pin is ignored.
0: MSB transmitted first
1: LSB transmitted first
2
It is not used in I S mode and SPI TI mode
0: Peripheral disabled
1: Peripheral enabled
When disabling the SPI, follow the procedure described in
000: f /2
PCLK
001: f /4
PCLK
010: f /8
PCLK
011: f /16
PCLK
100: f /32
PCLK
101: f /64
PCLK
110: f /128
PCLK
111: f /256
PCLK
They are not used in I
0: Slave configuration
1: Master configuration
2
It is not used in I S mode.
2
S mode
2
S mode and SPI TI mode
2
S mode and SPI TI mode
2
S mode.
2
S mode.
RM0033 Rev 9
RM0033
Section 25.3.8
.