ST STM32F207 Series Reference Manual page 57

RM0033
configured, you can check the AHB prescaler factor and clock source status values. To
make sure that the number of WS you have programmed is effective, you can read the
FLASH_ACR register.
The FLASH_ACR register is used to enable/disable the acceleration features and control
the Flash memory access time according to CPU frequency. The tables below provides the
bit map and bit descriptions for this register.
For complete information on Flash memory operations and register configurations, please
refer to the STM32F20x and STM32F21x Flash programming manual (PM0059).
Flash access control register (FLASH_ACR)
The Flash access control register is used to enable/disable the acceleration features and
control the Flash memory access time according to CPU frequency.
Address offset: 0x00
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
15 14 13 12
DCRST ICRST
Reserved
rw
Bits 31:11 Reserved, must be kept cleared.
Bit 12 DCRST: Data cache reset
Bit 11 ICRST: Instruction cache reset
Bit 10 DCEN: Data cache enable
Bit 9 ICEN: Instruction cache enable
27 26 25
11 10 9
DCEN ICEN
w rw rw
0: Data cache is not reset
1: Data cache is reset
This bit can be written only when the D cache is disabled.
0: Instruction cache is not reset
1: Instruction cache is reset
This bit can be written only when the I cache is disabled.
0: Data cache is disabled
1: Data cache is enabled
0: Instruction cache is disabled
1: Instruction cache is enabled
24 23 22
Reserved
8 7 6
PRFTEN
Reserved
rw
RM0033 Rev 9
Memory and bus architecture
21 20 19 18
5 4 3 2
rw
17 16
1 0
LATENCY
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