ST STM32F207 Series Reference Manual page 103

RM0033
Bit 10 HSIRDYIE: HSI ready interrupt enable
Bit 9 LSERDYIE: LSE ready interrupt enable
Bit 8 LSIRDYIE: LSI ready interrupt enable
Bit 7 CSSF: Clock security system interrupt flag
Bits 6
Bit 5 PLLI2SRDYF: PLLI2S ready interrupt flag
Bit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag
Bit 3 HSERDYF: HSE ready interrupt flag
Bit 2 HSIRDYF: HSI ready interrupt flag
Bit 1 LSERDYF: LSE ready interrupt flag
Set and cleared by software to enable/disable interrupt caused by the HSI oscillator
stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Set and cleared by software to enable/disable interrupt caused by LSI oscillator
stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Reserved, always read as 0.
Set by hardware when the PLLI2S locks and PLLI2SRDYDIE is set.
Cleared by software setting the PLLRI2SDYC bit.
0: No clock ready interrupt caused by PLLI2S lock
1: Clock ready interrupt caused by PLLI2S lock
Set by hardware when PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Set by hardware when External High Speed clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Set by hardware when the Internal High Speed clock becomes stable and HSIRDYDIE is
set.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI oscillator
1: Clock ready interrupt caused by the HSI oscillator
Set by hardware when the External Low Speed clock becomes stable and LSERDYDIE is
set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
RM0033 Rev 9
Reset and clock control (RCC)
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