ST STM32F207 Series Reference Manual page 942

Ethernet (ETH): media access control (MAC) with DMA controller
transmit DMA. You can issue this command anytime and the TxDMA resets it once it starts
re-fetching the current descriptor from host memory.
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Bits 31:0 TPD: Transmit poll demand
EHERNET DMA receive poll demand register (ETH_DMARPDR)
Address offset: 0x1008
Reset value: 0x0000 0000
This register is used by the application to instruct the DMA to poll the receive descriptor list.
The Receive poll demand register enables the receive DMA to check for new descriptors.
This command is given to wake up the RxDMA from Suspend state. The RxDMA can go into
Suspend state only due to the unavailability of descriptors owned by it.
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Bits 31:0 RPD: Receive poll demand
Ethernet DMA receive descriptor list address register (ETH_DMARDLAR)
Address offset: 0x100C
Reset value: 0x0000 0000
The Receive descriptor list address register points to the start of the receive descriptor list.
The descriptor lists reside in the STM32F20x and STM32F21x's physical memory space
and must be word-aligned. The DMA internally converts it to bus-width aligned address by
making the corresponding LS bits low. Writing to the ETH_DMARDLAR register is permitted
only when reception is stopped. When stopped, the ETH_DMARDLAR register must be
written to before the receive Start command is given.
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When these bits are written with any value, the DMA reads the current descriptor pointed to
by the ETH_DMACHTDR register. If that descriptor is not available (owned by Host),
transmission returns to the Suspend state and ETH_DMASR register bit 2 is asserted. If the
descriptor is available, transmission resumes.
When these bits are written with any value, the DMA reads the current descriptor pointed to
by the ETH_DMACHRDR register. If that descriptor is not available (owned by Host),
reception returns to the Suspended state and ETH_DMASR register bit 7 is not asserted. If
the descriptor is available, the Receive DMA returns to active state.
TPD
rw_wt
RPD
rw_wt
SRL
RM0033 Rev 9
9 8 7 6 5 4 3
9 8 7 6 5 4 3
9 8 7 6 5 4 3
RM0033
2 1 0
2 1 0
2 1 0