Nortel DMS-10 Series Installation, Operation And Maintenance Manual page 137

Table 3-2
Description of ERRMAP Entries
EVT#, message, alarm, level
08, DMA COMM FAIL
Major, 2
09, PROC STAT ALARM
Major, 2
10, PROG CKSUM ALM
Major, 3
BMC II BISYNC Operation, Administration, and Maintenance Guide BMCB001 and up
Section 060-INDP-310 System Administration Guide 3-19
Comments
Cause:DMA timeout
Test:checked every 16 msecs
Reset:no automatic reset, cleared by input of RSERR command
Notes:when the TEC/DSI PCA transfers call record blocks through
the DMA channel, BMC sets up a time out value. At the end of the
timer count down, DMA time out occurs if the DMA has not
generated the interrupt to indicate completion of the DMA transfer
Cause:a.Counter Timer Chip (CTC) counter error
b.bad error control I/O status byte (ERIOST), status bit 1 is set
Test:when doing processor switch
Reset:no automatic reset, cleared by input of RSERR command
Notes:if alarm is set by bit 1 of ERIOST, no message is printed
Cause:static RAM software checksum error
Test:a.checksum test is continuously performed by a scheduled
call; one cycle takes about six minutes
b.one-time test after booting the program from disk to RAM
Reset:no automatic reset, cleared by input of RSERR command.
Alarm returns if condition persists
Sheet 3 of 10