Software Standby Control Register (Sbycr); Software Standby Control Register - Hitachi H8/500 Series Hardware Manual

Table 18-2 Software Standby Control Register
Name

Software standby control register

In the software standby mode, the CPU, clock, and the on-chip supporting module functions all
stop, reducing power consumption to an extremely low level. The on-chip supporting modules
and their registers are reset to their initial state, but as long as a minimum necessary voltage
supply is maintained (at least 2V), the contents of the CPU registers and on-chip RAM remain
unchanged. The I/O ports also remain in their current states.

18.3.2 Software Standby Control Register (SBYCR)

Bit
Initial value
Read/Write
The software standby control register (SBYCR) is an 8-bit register that controls the action of the
SLEEP instruction.
Bit 7—Software Standby (SSBY): This bit enables or disables the transition to the software
standby mode.
Bit 7
SSBY Description
0 The SLEEP instruction causes a transition to the sleep mode. (Initial value)
1 The SLEEP instruction causes a transition to the software standby mode.
The watchdog timer must be stopped before the chip can enter the software standby mode. To
stop the watchdog timer, clear the timer enable bit (TME) in the watchdog timer's timer
control/status register (TCSR) to 0. The SSBY bit cannot be set to 1 while the TME bit is set to 1.
When the chip is recovered from the software standby mode by a nonmaskable interrupt (NMI),
the SSBY bit is automatically cleared to 0. It is also cleared to 0 by a reset or transition to the
hardware standby mode.
Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 1.
Downloaded from Elcodis.com electronic components distributor
Abbreviation
SBYCR
7 6
SSBY —
0 1
R/W —
R/W
R/W
5 4 3
— — —
1 1 1
— — —
309
Initial Value Address
H'7F H'FFFB
2 1
— —
1 1
— —
0
—
1
—