Vr_Port; Vdpll And Avdx; Flash Media Socket Power; Table 3 - Texas Instruments PCI7620 Implementation Manual

SCPU019

2.3.2 VR_PORT

A 0.1-µF bypass capacitor is required on the VR_PORT terminal for decoupling.

Table 3.

Supply V
CC
VR_EN
Internal 3.3 V GND
External 3.3 V

2.3.3 VDPLL and AVDx

A parallel combination of high frequency decoupling capacitors near each terminal is suggested,
such as 0.1 µF and 0.001 µF. Lower frequency 10-µF filtering capacitors are also
recommended.

2.3.4 Flash Media Socket Power

A parallel combination of a 0.01-µF capacitor and a 10-µF capacitor placed on the power source
close to the flash media socket is recommended.
10 PCI7620/PCI7420/PCI6620/PCI6420 Implementation Guide

Requirements for Internal/External 1.8-V Core Power Supply

VR_PORT
1.8-V output Internal 1.8-V LDO-VR is enabled. This output is not for external use.
V 1.8-V input Internal 1.8-V LDO-VR is disabled. An external 1.8-V power supply, of
CC
minimum 50-mA capacity, is required.
Note